Electronic Design Engineer 2 (Job ID# 9539340)

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Qorvo US Inc., has a position in Chandler, Arizona.

Electronic Design Engineer 2: DUTIES -Verilog design of digital control

logic for mobile phone LNAs, TX controllers and switches. This

specifically involves working with and/or having knowledge of design and

timing closure (TCL layout setup script generation, setup/hold/width

timing violation fixing) using Cadence Innovus are required; RTL-to-GDS

flow, area optimization, and DRC/LVS error resolution; digital synthesis

using Cadence Genus or Synopsys Design Compiler and timing constraint

generation in TCL; Verilog digital design and verification and

understanding of Verilog/System Verilog syntax; understanding of

verification test benches, clocking and auto-checking; performing

verification on the Verilog code using simulation tools; and Python

Scripting And Other Scripting Languages. Additionally, Responsibilities

include the creation of test benches and verification through simulation

of the above designs using Xcelium, Verilog and Python automation;

constraint creation and synthesis of mobile phone digital circuit

designs with Cadence Genus, Conformal; and physical design and timing

closure of mobile phone digital circuit designs with Cadence Innovus.

Further, the responsibilities include script automation development with

Python to aid in the design of Qorvos mobile designs.

Hybrid: 3 days

in the office and 2 work from within reasonable commuting distance from

the office.

• MINIMUM REQUIREMENTS : Masters degree in Electrical Engineering and 6

months of experience, an internship, co-op, or 6 graduate credit hours

to involve knowledge of: (1) design and timing closure (TCL layout setup

script generation, setup/hold/width timing violation fixing) using

Cadence Innovus are required; RTL-to-GDS flow, area optimization, and

DRC/LVS error resolution; (3) digital synthesis using Cadence Genus or

Synopsys Design Compiler and timing constraint generation in TCL; (4)

Verilog digital design and verification and understanding of

Verilog/System Verilog syntax; (5) understanding of verification test

benches, clocking and auto-checking; (6) performing verification on the

Verilog code using simulation tools; and (7) Python scripting and other

scripting languages. Hybrid: 3 days in the office and 2 work from

within reasonable commuting distance from the office. Application Instructions: Send Resume to: ***email_hidden***

include Job Ref# 9539340** in the subject line. EOE.