Senior Technical Architect

Maximum Salary (US): 192000Minimum Salary (US): 95000Job SummaryRTL Design Verification engineers to perform SoC leavel and block-level verification of IP components. The role involves validating functionality of IPs provided and ensuring readiness for SoC-level integration.Key Responsibilities• Perform RTL design verification for SoC & IP blocks:o FSM (Finite State Machine)o DAC-related logic (with model interaction)o Pattern memory / controller logico at the test chip top• Test chip integration (hard ip, pads, custom logic, clock, reset etc.)• Develop and execute comprehensive verification plans• Build testbenches and verification environments (directed + random testing)• Validate functional correctness and interface behaviour• Perform debug and root cause analysis of RTL issues• Ensure coverage closure and verification completeness• Work closely with PD and integration teams to enable smooth SoC integrationSkill Requirements• Strong experience in RTL Design Verification• Write SV RTL for custom logic at the test chip top (clock, reset, FSM etc.)• Good understanding of:o Digital design fundamentalso FSM-based architectureso IP/block-level verificationo Understanding of UPFOther Requirements• Testbench development• Functional verification methodologies• Debugging and RTL issue analysisProgramming / Tools• Working knowledge of:o SystemVerilog / Verilogo UVM or similar verification methodologies (preferred)o Scripting (Python/Shell – good to have)