Senior Staff/Principal Reliability Engineer

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Reliability Development Engineering General Summary The Reliability Engineering organization leads the definition and execution of reliability strategy for advanced semiconductor technologies, ensuring robust qualification and technology certification across devices, packages, and systems. The team applies deep expertise in device and interconnect reliability physics—including BTI, TDDB, HCI, electromigration, self‑heating, and wear‑out mechanisms—to assess design and process robustness for complex SoCs and advanced packaging architectures (2.5D/3D, TSV, chiplets). Working cross‑functionally with design, process, test, product, and program teams, the organization anticipates and mitigates reliability risks across the full product lifecycle while balancing performance, power, quality, schedule, and business objectives. As a technical authority, the team establishes scalable reliability best practices, provides expert judgment on critical trade‑offs and EM waivers, mentors engineers, and communicates clear reliability status and risk insights to senior leadership. Minimum Qualifications Bachelor's degree in Engineering, Material Science, Computer Science, or related field and 8+ years of Reliability Engineering experience (e.g., reliability analysis, stress testing) or related work experience. Master's degree in Engineering, Material Science, Computer Science, or related field and 7+ years of Reliability Engineering experience or related work experience. PhD in Engineering, Material Science, Computer Science, or related field and 6+ years of Reliability Engineering experience or related work experience. 3+ years in a technical leadership role with or without direct reports. (Applies only to positions with direct reports). Responsibilities Define foundry qualification reliability requirements and execute to tech certification for complex designs and advanced technologies. Lead reliability strategy and execution for high-impact products and programs, spanning devices, packages, and systems. Perform and guide advanced reliability analysis, including aging, wear-out, electromigration, and other mechanism-based modeling, to assess design and process robustness. Anticipate, identify, and mitigate non-obvious reliability risks across the full product lifecycle. Drive cross‑functional alignment with design, process, test, product, and program teams to meet aggressive schedules without compromising quality. Establish and improve organizational reliability processes and best practices that scale to future technology generations. Provide expert technical judgment on critical reliability trade‑offs, balancing performance, power, quality, schedule, and business considerations. Mentor and develop engineers; serve as a trusted technical authority and advisor for reliability across the organization. Communicate reliability status, risks, and strategic recommendations clearly to senior leadership and executive stakeholders. Qualifications 10–15 years of industry experience in semiconductor reliability engineering, technology development, or product qualification, supporting advanced CMOS nodes (Planar, FinFET, GAA). Deep expertise in intrinsic device and interconnect reliability physics and failure mechanisms, including BTI, TDDB, HCI, electromigration, self‑heating effects, and MOL/BEOL wear‑out. Hands‑on experience in designing reliability test structures for test‑chips, measuring reliability test structure data, and interpreting complex reliability data from mechanisms such as EM, BTI, and TDDB. Strong background in advanced packaging and heterogeneous integration reliability, including TSV‑based 2.5D/3D integration, chiplet architectures, and backside power delivery schemes. Demonstrated experience translating device‑ and process‑level reliability data into circuit‑ and system‑level reliability metrics for complex digital SoCs and platform‑level decision making. Drive cross‑functional design collaboration for reliability with design, process, and reliability teams. Proven experience reviewing and approving design waivers for electromigration violations in SoC designs, including on‑chip metal, bump, and ball interfaces. Advanced statistical analysis and lifetime modeling expertise (e.g., Weibull analysis, JMP, Minitab, large‑data correlation) used to inform qualification sign‑off and risk decisions. Recognized technical leadership with a track record of influencing design, process, and program decisions, mentoring engineers, and driving cross‑functional alignment across design, product engineering, test, and foundry teams. MS or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or related field (PhD preferred), with demonstrated industry impact in reliability or technology development. Benefits Competitive base salary commensurate with experience and level. Annual discretionary bonus program. Eligibility for annual RSU grants. Comprehensive benefits package designed to support success at work, at home, and at play. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e‑mail disability‑View email address on click.appcast.io or call Qualcomm’s toll‑free number for assistance. Pay range and Other Compensation & Benefits: $180,200.00 - $270,200.00 #J-18808-Ljbffr