Senior/Staff Front-End Design Engineer (RTL Design - RiscV)

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

• CPU Core Integration & Customization: Responsible for the integration of a commercial RISC-V core soft IP with external accelerators utilizing RISC-V custom extension instruction interfaces.
• Specification & Feature Tailoring: Perform feature tailoring of the CPU soft IP, configuring the microarchitecture to strip away unnecessary features and meet strict performance, power, and area (PPA) requirements.
• RTL Modification: Perform targeted Verilog/SystemVerilog RTL design modifications and enhancements, primarily focusing on the processor front-end and the control path to support customized architectural features.
• Cross-Functional Collaboration: Work closely with performance engineers, middle-end engineers, and back-end (physical design) engineers to ensure seamless IP integration, optimize system-level performance, and meet physical design constraints.
• ASIC Front-End Execution: Drive Front-End (FE) ASIC implementation steps, including supporting synthesis, static timing analysis (STA) closure, power reduction, and floorplanning efforts to optimize PPA.
• Verification & Debugging: Contribute to design verification (DV) efforts and assist in debugging complex logic issues across both pre-silicon and post-silicon stages.

• Education: Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with a strict focus on computer architecture.
• RISC-V Expertise: Familiarity with the RISC-V ISA, particularly custom extensions, extension instruction interfaces, privilege modes, and Control and Status Registers (CSRs).
• Core Integration & Architecture: Strong understanding of CPU architecture and logic design, with prominent, hands-on experience in CPU core integration , technical specification drafting, and IP feature tailoring/pruning.
• RTL Design: Extensive Verilog RTL development experience using industry-standard tools.
• Collaboration Experience: Proven working experience collaborating with performance modeling/engineering teams, middle-end engineers (synthesis/DFT), and back-end (P&R) engineers.
• Preferred Knowledge: (1) Synthesis flows, linting, CDC/RDC analysis, and static timing analysis (STA). (2) SoC-level power-saving techniques, clocking architectures, reset/power-up sequences, and low-power microarchitecture development. (3) DFT, DFX, MBIST techniques.
• Automation: Comfort with writing in scripting languages (Python, Perl, Shell, TCL) to automate design.

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.