Staff Thermal & Thermo-Mechanical Analysis Engineer - Contractor

Staff Thermal & Thermo-Mechanical Analysis Engineer - Contractor TylSemi, Inc. San Jose, California, United States About this position About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path. Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years: Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself. Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing. Culture & Team: How We Work No Politics, No Bureaucracy There are no layers, no approval chains, no corporate theater. If you have an idea, we test it. If it works, we ship it. No endless meetings, no PowerPoint presentations to convince middle management. Remote-Friendly, Global Team US team: Bay Area preferred, but we hire the best people regardless of location India team: Building a world-class design center in Bangalore Move Fast, Ship Real Products We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win. What We Value Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. Bias for action. We move fast. Analysis paralysis doesn't fly here. Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. Low ego, high standards. We don't care about titles or politics. We care about results. The Ask If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's why you should: The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk. READY TO JOIN? Role Overview We are seeking a staff-level Thermal & Thermo-Mechanical Analysis Engineer to lead the simulation, modeling, and architectural definition of our next-generation AI data center hardware . In this role, you will be responsible for the end-to-end thermal integrity of high-power AI systems. Your work will directly impact advanced CoWoS (Silicon Interposer) architectures, complex substrate packaging , and high-layer-count data center-class PCBs . The ideal candidate will possess deep expertise in semiconductor thermal management and will develop innovative cooling solutions spanning chip/package/PCB/system stack including traditional air cooling, cold plates, direct-to-chip liquid cooling, immersion cooling, microchannel cooling, advanced TIMs, and emerging thermal technologies required to support future AI compute platforms. What you'll do Thermal Analysis & Modeling: Build high-fidelity static and dynamic thermal models for AI workloads spanning silicon, advanced packaging, and system levels. Thermo-Mechanical Simulation: Predict and mitigate structural risks including warpage, die-tilt, thermal stress, and solder joint reliability (BLR/BGA). Workload-Driven Characterization: Simulate transient thermal behavior under varying data center workloads, calculating time-dependent nodal temperatures, and plotting thermal contours. Mitigation Strategies: Develop, propose, and implement innovative cooling and mechanical mitigation techniques (e.g., TIM selection, stiffener rings, optimized copper balancing). System level solution : Perform thermal modeling and CFD analysis for die, package, board, and system designs. Develop cooling solutions for high-power AI/HPC devices (>1kW TDP). Cross-Functional Collaboration: Partner with Silicon Architecture, Package Design, and System Hardware teams to co-optimize the thermal-mechanical-electrical envelope. E ngage with ODMs and cooling ecosystem partners What We're Looking For Experience: 5+ years of industry experience in thermal and structural analysis of semiconductor packages and systems. Advanced Simulation Tool Mastery: Proficient in industry-standard thermal and thermo-mechanical tools, specifically Ansys Icepak and Cadence Celsius . Fluent, Star-CCM+, FLOEFD, RedHawk-SC ET Advanced Packaging Expertise: Proven experience modeling high-density packaging architectures, specifically TSMC CoWoS-L (with Silicon Interposers). Substrate & PCB Knowledge: Deep understanding of complex package substrates and heavy data center-class PCBs . Data Center Experience: Hands-on experience analyzing high‑power GPU workloads (700W–1000W+) under both static steady‑state and dynamic transient states. Data Visualization: Ability to extract, analyze, and present complex simulation metrics, including multi‑layer thermal contours and structural warpage profiles. Good to Have Package Design Capabilities: Hands‑on experience designing physical package layouts and substrate routing using Cadence APD (Allegro Package Designer) or Allegro X. Multi-Physics Integration: Familiarity with structural analysis tools like Ansys Mechanical for deep‑dive finite element analysis (FEA). #J-18808-Ljbffr