Senior ASIC Digital Architect DDR/PCIe/UCIe Leader (Equity)
Synopsys
Synopsys is seeking an experienced ASIC Digital Architect to define RTL design and verification at chip/block levels. You will lead designs for DDR, PCIe, CXL, UAL, and UCIe protocols, collaborating across teams to ensure high-quality results. You will mentor engineers, drive best practices, and communicate complex technical concepts to stakeholders while influencing strategic project directions. #J-18808-Ljbffr Synopsys
Vacancy posted 1 day ago
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