Staff Engineer, ASIC Design Verification

San Jose, California, United States Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together: Our technology solutions power the tools you use every day— including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities. The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions such as Custom HBM base die, AI accelerators. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production. Job: 42935 Location: Daily onsite presence in San Jose HQ or Folsom location 5 days week What You’ll Do Participate in verification strategy and methodology definitions Contribute in micro architecture specification and reviews Responsible for the verification of modules/subsystems of AI accelerators Execute the verification per plan to the closure Work closely with architects and design engineers to define verification requirements, and to close functional and code coverage targets. Provide support in post silicon bring up and debug What You Bring BE (MS preferred) in Computer/Electrical Engineering or Computer Science with 10+ years working experience in ASIC verification preferred. Experience in UVM Strong language skills including C++, SystemVerilog Experience in logic and SoC verification from planning to closure Good understanding on verification flows and tools Experience in UCIe, HBM controller, Memory DFT. Preferred Skills Experience in DDR and Custom HBM and related IP level and/or SOC level verification Experience and/or knowledge of the emerging technologies (CXL, Computation in memory and storage, AI LLM accelerators etc.) in server memory and storage systems Highly motivated with good verbal and written communication skills Creativity in problem solving You’re inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change Base Pay Range

$163,000 - $253,000 USD

Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. #J-18808-Ljbffr Conductor