Staff Physical Design Engineer, HBM

Req ID: JR93211 Staff Physical Design Engineer, HBM Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. You will lead the physical implementation of High Bandwidth Memory (HBM) products that power artificial intelligence (AI), high‑performance computing (HPC), and data center systems. You’ll shape physical architecture and execution from early design through tape‑out, with a direct impact on first‑pass silicon success. This role offers broad technical ownership, multi-functional influence, and visibility at the most advanced process and packaging nodes. Responsibilities Lead end‑to‑end physical design for HBM base and memory dies from netlist through GDSII (Graphic Data System II), including floorplanning, power planning, placement, clock tree synthesis, routing, and signoff. Define and drive HBM‑specific physical architecture, including channel partitioning, physical layer (PHY) placement, through‑silicon via (TSV) keep‑out regions, and die‑to‑package co‑design alignment. Optimize bandwidth, latency, power, and yield by partnering closely with memory architecture, PHY, register‑transfer level (RTL), synthesis, design‑for‑test (DFT), and packaging teams. Design and validate the power delivery network, ensuring current integrity, electromigration (EM), and thermal closure across all operating modes. Drive timing closure across corners for high‑speed logic and HBM interfaces, addressing signal integrity, noise, and crosstalk. Ensure physical signoff readiness, including static timing analysis, power integrity, signal integrity, design rule checks, layout versus schematic, density, and reliability compliance. Lead engineering change order strategies, improve flows and automation, and contribute to scalable HBM physical design methodologies. Mentor engineers and represent physical design in tape‑out reviews and executive‑level technical discussions. Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or an equivalent level of experience. 12+ years of hands‑on experience in advanced‑node physical design with proven tape‑out success on HBM, dynamic random‑access memory (DRAM), or large memory‑centric designs. Deep expertise in hierarchical physical design, timing closure, static timing analysis, power integrity, thermal analysis, and physical signoff. Expert‑level experience with Cadence Innovus and/or Synopsys IC Compiler II (ICC2) or Fusion Compiler, plus power integrity tools such as Voltus or RedHawk. Experience with foundry signoff flows, including design rule checking and layout versus schematic verification. Preferred Qualifications Experience with HBM2E, HBM3, or HBM3E products and TSV‑based designs, including micro‑bump layouts. Exposure to die‑to‑die interfaces, wide parallel buses, and advanced packaging approaches such as 2.5D interposers and chiplet‑based designs. Background in signal integrity considerations for dense, high‑speed memory systems. Strong scripting skills using Tcl or Python to automate and scale physical design flows. Experience supporting system‑level integration with graphics processing units, accelerators, or system‑on‑chip designs. Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr Micron Technology, Inc