Wafer Architect: AI Chip System Lead (Multi‑Die)
Conductor
Conductor seeks an architect to own the logical architecture for the A-0 and A-1 wafer products. You will collaborate with the XPU/Compute chip architect and memory architect to synthesize the final wafer-level architecture. The ideal candidate has deep hands-on experience in AI chip design (GPUs, TPUs, XPUs, ASICs) and strong knowledge of memory subsystems in multi-die configurations, with an emphasis on LLM inference workloads from software to hardware implications. #J-18808-Ljbffr Conductor
Vacancy posted 4 days ago
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