Strategic DRAM IO/Clock Design Architect (Boise)
Micron Technology Inc
Micron Technology, Inc. in Boise, Idaho, invites an experienced Principal/ MTS IO/Clock Design Engineer to join the DRAM IP Design team. You will design, verify and optimize high-speed IO and clock circuits for Micron's DRAM products, focusing on equalization, timing, jitter, and system timing.
Relocation to Micron headquarters in Boise is required. You will collaborate across product engineering, SI, and process teams, mentor engineers, and pioneer AI-assisted design flows to push circuit
#J-18808-Ljbffr- ...Micron Technology, Inc. seeks a Principal/Member of Technical Staff (MTS) IO/Clock Design Eng to join the DRAM IP Design team for high-speed IP circuits used in Micron's DRAM products. Relocation to Boise, Idaho is required; you will develop, verify, and optimize IO and...SuggestedFull timeRelocation
- ...Technology, Inc. seeks an experienced high-speed IO/clocking design engineer at the Principal/Sr Staff level to advance DRAM IP. You will own architecture, design,... ...equalization, bandwidth, timing and jitter; relocation to Boise is required. You will drive modeling and...SuggestedFull timeRelocation
- ...Technology, Inc is seeking a Principal SMTS for DRAM IP design to architect, design and verify high-speed IO and clocking circuits for next‑generation DRAM products,... ...timing, jitter, and signal integrity. Relocation to Boise, ID is required; the role involves...SuggestedFull timeRelocation
- ...are seeking a Principal/Member of Technical Staff (MTS) IO/Clock Design Engeer to join our DRAM IP Design team and contribute to the development of critical... ...challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities...SuggestedFull timeLocal areaImmediate startRelocation
$135k - $286k
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$162k - $235k
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