Staff HBM Design Architect - DFT

As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. Responsibilities Define and implement end‑to‑end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked‑die, cube‑level, and system‑level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts Experience with wafer probe and final test semiconductor flows 5+ years of experience in DRAM or ASIC DFT design or verification Preferred Qualifications Experience with HBM, DRAM, or advanced memory products Knowledge of TSV‑based 3D integration and stacked‑die test challenges Hands‑on experience with at‑speed test or advanced DFT techniques Exposure to DFT security features or custom customer test interfaces Salary US base salary range: $146,000.00 – $297,000.00 per year. Additional compensation may include benefits, bonuses, and equity. Equal Opportunity Employer Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr 1000 Micron Technology, Inc.