ASIC verification Engineer

Minimum Requirements At least 4 years of experience with pre-silicon DV (Design Verification) Hands‑on experience writing code using System Verilog and UVM for the past 2 years Quick learner, independent, and good communicator Knowledge and hands‑on experience with Verilog, System Verilog, UVM, debugging waveforms Proficient in building a testbench for a medium‑complexity block using System Verilog and UVM Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM. Developing, maintaining and supporting the UVM verification environment. Debugging tests with design engineers to deliver functionally correct design blocks. OOPs, randomization, constraints, interfaces. Writing & analyzing functional coverage, assertions. Generating and analyzing code coverage & writing waivers. Desired Skills/Qualifications Experience with verification of networking products and networking background. Experience with DMA based verification. Qualified candidates should send their resume and application to: View email address on click.appcast.io #J-18808-Ljbffr