Senior ASIC Design Architect: DDR/PCIe Innovation Lead

Synopsys is seeking an experienced ASIC Digital Architect based in Austin, Texas. This role focuses on defining and developing ASIC RTL designs, particularly for DDR, PCIe, and UCIe protocols. The candidate will lead design efforts, collaborate with cross-functional teams, and mentor junior engineers to foster innovation within the team. Candidates should possess extensive experience in ASIC design, strong problem-solving skills, and excellent communication abilities. Join Synopsys to contribute to cutting-edge semiconductor technology with a focus on continuous improvement and excellence. #J-18808-Ljbffr Synopsys