CPU Cache RTL Architect - High-Performance Microarchitecture
Apple Inc.
A leading technology company in Santa Clara is seeking an experienced engineer to join its Silicon Engineering Group. The role involves micro-architecture development, driving CPU multi-level cache architecture, and RTL design for multi-processor systems. Candidates should have a BS degree and at least 3 years of relevant experience, particularly in microprocessor architecture and logic design principles. Experience with Verilog/VHDL is essential, along with the ability to support verification processes. #J-18808-Ljbffr Apple Inc.
Vacancy posted 3 days ago
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