Quantum Cryo CMOS Design Enablement

Quantum Cryo CMOS Design, Sr. Manager / Deputy Director

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets.

The Sr. Manager / Deputy Director for Quantum Cryo CMOS Design is a senior technical and organizational leadership role responsible for establishing cryogenic CMOS design enablement capability to support quantum technologies. This role combines deep technical expertise in device modeling, design enablement, and cryogenic characterization with strong people leadership to establish the strategy, infrastructure, and team required to deliver Process Design Kits (PDKs) that translate advanced device physics into scalable, manufacturable, and customer-usable design solutions.

This role owns the end-to-end design enablement strategy for cryogenic CMOS platforms, including PDK development, model development, test infrastructure, and EDA engagement, while leading a multidisciplinary team spanning modeling, characterization, test chip design, and other design enablement engineering functions. As a Sr. Manager / Deputy Director, the position serves as a primary interface across technology development, design enablement, EDA partners, and customers, ensuring that cryogenic and quantum technologies are fully enabled through accurate models, validated design flows, and production-ready PDKs aligned with system, program, and customer requirements.

Essential Responsibilities:

• Define and lead the cryogenic CMOS design enablement roadmap, including PDK development, model creation, and design methodologies.
• Build, lead, and develop a high-performance team spanning device modeling, test, characterization, and design enablement engineering.
• Drive development of cryogenic CMOS PDKs, including compact models, variability models, parameter extraction, and validation methodologies.
• Establish cryogenic test lab capabilities, including test infrastructure, measurement techniques, and data pipelines for model development and validation.
• Define and implement electrical characterization methodologies and test structures to support accurate model extraction and correlation to silicon data.
• Oversee test chip design and execution to enable continuous improvement of models, design rules, and PDK deliverables.
• Partner with EDA vendors to develop and deploy new capabilities, design flows, and simulation methodologies required for cryogenic and quantum design enablement.
• Drive cross-functional execution across device engineering, process development, integration, and design enablement teams to translate technology into usable design collateral.
• Define technical milestones, success criteria, and deliverables, and communicate progress, risks, and mitigation plans to leadership and stakeholders.
• Serve as a senior technical and organizational interface with customers, partners, research institutions, and externally funded programs.

Required Qualifications:

• Education: MS or PhD in Electrical Engineering, Physics, Applied Physics, or related field
• Years of Experience: 12
• Percentage of travel: 15%

Preferred Qualifications:

• Experience with cryogenic electronics, quantum computing hardware, or low-temperature device physics
• Experience building or scaling test labs and measurement infrastructure
• Experience working with EDA vendors
• Knowledge of variability modeling, statistical modeling, and simulation
• Experience with government, academic, or industry research collaborations
• Track record of setting technical direction and mentoring senior engineers

Expected Salary Range: $143,000.00 - $247,000.00. The exact salary will be determined based on qualifications, experience, and location.