Senior Physical Design Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAian, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Job Overview NVIDIA is looking for best‑in‑class Senior Physical Design Engineers to join our Networking Silicon engineering team, developing the industry's best high‑speed communication devices and delivering the highest throughput and lowest latency. You will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets, working at the partition and chiplet level. Key Responsibilities Participate in establishing physical design methodologies and flow automation. Develop chip floorplan and power/clock distribution plans. Support chip assembly and placement & route (P&R). Achieve timing closure. Engage in all aspects of physical chip development (RTLtoGDS) including trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification. Assist in design flow development and debugging, including the application of ML/AI solutions. Provide expertise in RC extraction, correlation, tape‑out solutions, and other physical verification tasks. Qualifications BSEE / MSEE or equivalent experience. At least 5 years of experience in VLSI physical design implementation on 5nm, 4nm, and 3nm technology. A proven track record of delivering designs to production. Deep experience in timing closure, clock/power distribution and analysis, RC extraction, place & route, and tape‑out solutions. Validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, and major EDA tools such as Synopsys (ICC2, DC, PT, STAR, ICV) and Cadence (Genus, Innovus, Tempus). Strong analytical and debugging skills. Proficiency in Python, Perl, Tcl, or Make scripting is helpful. Excellent teamwork and communication skills. Benefits and Compensation Base salary range for Level3: $136,000 – $218,500 USD. Base salary range for Level4: $168,000 – $264,500 USD. Eligible for equity and benefits. Salary is based on location, experience, and comparable positions. Equal Opportunity Statement NVIDIA is committed to fostering an inclusive work environment and is an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Corporation