CPU CDC/RDC/STA Engineer
Apple Inc.
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Description In this role, you will be: Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the importance of structurally safe solutions to each issue Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs including things needed to complement CDC/RDC Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems Working closely with EDA vendor representatives to drive improvements and new methodologies Working closely with RTL, Verification, CAD, and Physical Design teams Minimum Qualifications Minimum BS and 10+ years of relevant industry experience Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC) Experience with at least one of the following: Synopsys or Real Intent tool Scripting experience in TCL or Perl Experience in Verilog Preferred Qualifications Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations Experience in multi-clock-domain RTL design Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong. Learn about accessibility in Apple’s workplace Learn about reasonable accommodations for job applicants Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr Apple Inc.
- Apple Inc. in Santa Clara is seeking a senior hardware verification engineer to own the CDC/RDC sign-offs for CPU designs, collaborate with RTL and DV teams, and drive robust STA checks across multi-clock domains. The role requires deep Verilog/SystemVerilog expertise,...Suggested
$167.7k - $245.2k
...development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with... ....Your role may include SDC validation, CDC check, and SDC flow development.Developing... ...working experience with RTL design, CDC/RDC and conformal verification, SDC development...SuggestedFull timeTemporary workWork experience placementLocal areaFlexible hoursShift work- ...products that empower the world of Communication, Networking, CPU/Servers, Automobile, Bio-Medicals, Consumer Electronics and a wide... ...has operations in India & APAC. Job Description Job Profile: STA Engineer Experience: 10+ Years Duration: 12+ Months Location: Sunnyvale,...SuggestedFlexible hours
- ...and beyond. Together, we advance your career. THE ROLE: The STA/Constraints Engineer is responsible for developing FullChip constraints and timing... ...timing closure and constraints methodology. Responsible for cdc/lint, timing closure, lower power implementation and netlist...SuggestedWorldwideShift work
$100k
...team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build... ...contributors of all seniorities.We are looking for a talented engineer to join our CPU design team to define and implement RTL for high...SuggestedPermanent employment$198.7k - $298.1k
Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > CPU EngineeringGeneral Summary:We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low-power devices. In this role, you will contribute to architecture...Work experience placementWork from home$158.76k - $194.04k
...‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer to design industry‑leading CPU and interconnect IP, enabling rapid adoption of RISC‑V... ...SystemVerilog, or VHDL. Strong grasp of RTL quality checks (Lint, CDC, RDC, etc.). Hands‑on experience with Spyglass is a plus....Flexible hours- CPU Physical Design and Integration Engineer Santa Clara, California, United States Hardware Imagine what you could do here. At Apple, new ideas have a way... ...CMOS circuit design. Working knowledge of extraction, STA, EMIR concepts. Ability to work well in a team, being...Relocation
$152k - $241.5k
We are currently seeking a Senior Developer Technology Engineer, CPU Performance!Would you enjoy researching new algorithms and discovering new techniques to optimize data intensive applications? Do you like investigating hardware and system bottlenecks, and optimizing...Full timeRemote work$153.2k - $229.8k
...Responsibilities Timing Analysis: Drive subsystem‑level STA and timing closure for both pre‑layout... ...(AXI/AHB) and clock domain crossing (CDC). Exposure to physical design flows.... ...Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design...Work experience placementWork from home- Qualcomm in Santa Clara is seeking engineers to advance CPU performance modeling, microarchitecture and RTL implementation. You will collaborate with the CPU team to explore high-performance strategies and refine RTL to meet timing, area and power goals. The role also...
- Apple Inc. in Cupertino seeks an ASIC STA Engineer to lead timing closure across complex SoCs. You will own timing closure for full chips and blocks, guiding timing verification and constraint generation across projects. Work with multi-functional teams to resolve timing...
- Apple Inc. in Santa Clara, California, is seeking a CPU Design Timing Engineer to own the timing closure of the project. You will work with the CAD team to develop the timing flow, including scripting to improve analysis flows and engineer efficiency, and collaborate with...
$198.7k - $298.1k
...exploration. Explore high performance strategies working with the CPU performance modeling team. Microarchitecture development and... ...performance goals. Design delivery. Work with multi‑functional engineering team to implement and validate physical design on the aspects of...Work experience placementWork from home- ...transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team... ...for the high quality IP deliverables. Description As an ASIC STA Engineer, you will have responsibilities spanning various...Full time
$167.1k - $250.7k
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, CPU Engineering General Summary: RISC-V CPU Compiler Engineer Job Description Are you passionate about maximizing CPU performance and pushing the boundaries of optimization? Join our innovative team...Work experience placementWork from home$167.1k - $250.7k
Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > CPU EngineeringGeneral Summary:NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity...Work experience placementWork from homeWorldwide$168k - $264.5k
At NVIDIA, we are redefining the future of computing! As a Senior Verification Engineer on our CPU Verification Team, you will play a pivotal role in our mission to push the frontiers of technology. Your work here will impact a broad array of products, from consumer graphics...Full timeWork experience placement- ...methods and strategies; preferable in-depth experience in top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesis;... ...and Methodology Development Collaborating with IC Design RTL Engineers Required Skills: TCL/PERL Scripting Proficiency in...
$165k - $241.4k
...networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography... ..., and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and...Full timeTemporary workWork at officeLocal areaFlexible hours- Insilico is seeking an experienced STA Engineer to join their team in Sunnyvale, CA. The ideal candidate should have over 10 years of experience in Static Timing Analysis and demonstrate proficiency with tools such as Synopsys DC and Cadence conformal. Your role will involve...
$168k - $264.5k
...and motivated Implementation Methodology Engineer for NVIDIA's elite VLSI team. This role involves... ...be realized in the world’s most advanced CPU silicon! If you are a hands-on technical... ..., placement, CTS, routing, and MCMM STA.EDA Tool Proficiency: Power user of synthesis...Full time$136k - $218.5k
NVIDIA is looking for a Senior CPU Tooling and Design Automation Engineer! Do you want to help drive the development of CPU technology for architectures used for artificial intelligence (AI) / deep learning (DL), high-performance computing (HPC), cloud service providers...Full timeWork experience placementNight shift$110k - $145k
...bottlenecks across the chip development lifecycle—such as DRC/CDC/STA debug, regression triage, PPA convergence, and ECO iteration.... ...versus internal implementationsRequirements:BS or MS in Electrical Engineering, Computer Science, or equivalent industry experience2+ years...$138k - $197k
...full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee final timing signoff for SoCs.Minimum qualifications:Bachelor's degree in Electrical...Full timeWorldwide$167.1k - $250.7k
...Requirements: We require a bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus... ...prefer candidates who have led a small verification team focused on CPU verification. Knowledge of advanced techniques such as...Full timeWork from home- Apple Inc. in Santa Clara, CA is seeking a CPU Physical Design and Integration Engineer to join the hardware team. You will lead physical design, integration, and verification for high‑performance processors, drive tape‑out sign‑off, and collaborate across Implementation...
$214.1k - $309.8k
...member of the team, you will contribute to defining innovative ASIC STA methodologies and creating robust flows essential for... ...a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products...Full timeTemporary workLocal areaFlexible hours- ...NVIDIA is seeking a Senior CPU Tooling and Design Automation Engineer to advance CAD tool development for CPU/ Fabric teams and to create NoC/SoC tooling that boosts productivity across design teams. You will work closely with architects, chip leads, and designers to...Night shift
- Qualcomm Atheros, Inc. is seeking a senior role focused on static timing analysis, synthesis, and low‑power implementation for complex WiFi SoCs. The position requires hands‑on experience with PrimeTime, Design Compiler, Genus, and multi‑corner/multi‑mode timing closure...
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