Lead SERDES RTL Design Engineer

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At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

SerDes Technology group is seeking a talented, motivated and self‑driven SerDes Micro Architect with expertise in high‑speed SerDes RTL design. You have had significant success driving architecture and product requirements, integrating complex IPs into SOC. You have deep knowledge of digital design methodology and are meticulous about Power, Performance and Area. In this role, you will work with a world‑class team to drive the definition of next generation high‑speed SerDes IPs.

THE PERSON:

If you have a keen interest in high‑speed SerDes and digital RTL design, excel in teamwork and possess strong communication skills, your profile aligns well with our requirements. We are seeking someone who is innovative, detail‑oriented and possesses excellent problem‑solving skills to join our design team.

KEY RESPONSIBILITIES:

Define micro‑architecture requirements for SerDes IPs, drive technical specifications to meet those requirements, and provide technical direction to execution teams Design and development of digital logic blocks in leading edge technology nodes Work with cross‑functional teams to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Work closely with design teams for area and floorplan refinement, verification test plan reviews, timing targets, emulation plans, pre‑Si bug resolution and performance/power verification sign offs Support post‑Si teams for product performance, power and functional issues debug/resolution

PREFERRED EXPERIENCE:

Excellent communication, management, and presentation skills Adept at collaboration among top‑thinkers and senior architects with strong interpersonal skills to work across teams in different geographies Experience in driving the definition of high‑speed SerDes IPs, with strong knowledge on the application in PCIe and Ethernet Experience in system architecture, CPU & IP Integration, power and clock management design Experience in RTL design, verification, synthesis and STA in high performance design Good understanding of adaptation and calibration algorithms Good understanding of link equalization, clock and data recovery Good understanding of digital signal processing Good knowledge of SystemVerilog and UVM

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree in related discipline

LOCATION:

San Jose, CA

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Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr Advanced Micro Devices