Physical Design Engineer

Physical Design Engineer

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Role and Impact: Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of custom IP and SoC designs. As part of our dynamic team, you will work on cutting-edge technology to implement designs from RTL to GDS, ensuring they are ready for manufacturing. Your contributions will directly influence the optimization of critical product parameters such as power, frequency, and area, supporting Intel's mission to deliver innovative and high-performance solutions to the market. This position offers an exciting opportunity to drive meaningful advancements in physical design methodologies and automation while collaborating with industry-leading experts.

Key Responsibilities:

• Perform physical design implementation of custom IP and SoC designs, covering all aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution.
• Conduct verification and signoff processes, including formal equivalence verification, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyze results and recommend fixes for violations to meet product design specifications and future architecture goals.
• Optimize designs to enhance product-level parameters such as power, frequency, and area.
• Develop and improve physical design methodologies and flow automation to achieve higher efficiency and scalability.
• Collaborate with multi-disciplinary teams to address challenges in areas such as timing closure, physical clock design, multiple power domain analysis, and DFT implementation.
• Utilize industry-standard EDA tools to ensure high-quality design implementation and validation.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field of study with 3+ years of hands-on experience in physical design implementation for custom IP or SoC designs OR a Master's degree in Electrical Engineering, Computer Engineering, or a related specialized field of study with 2+ years of hands-on experience in physical design implementation for custom IP or SoC design.
• Proficiency in industry-standard EDA tools for synthesis, place and route, timing analysis, and layout verification.
• Experience in physical design flows, including clock tree synthesis, floor planning, timing closure, and power integrity analysis.

Preferred Qualifications:

• Physical design experience in integrated circuit design tools including logic synthesis, place and route, static timing analysis and design closure
• Design experience with RTL design, and a thorough knowledge of timing closure processes to effectively analyze and optimize semiconductor device performance
• Experience with scripting in an interpreted language (TCL)
• Strong problem-solving and analytical abilities

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Massachusetts, Beaver Brook

Additional Locations

US, Arizona, Phoenix

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.