Analog IP Design Execution Manager

Hard IP and Test Chip Development Team The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry-defining analog and mixed-signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die‑to‑die interfaces across multiple advanced process nodes. As an IP execution leader, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology. Responsibilities All aspects of integrated IP planning, execution, and delivery from initial engagement with SOC partners through launch. Coordinate across IP domains (architecture, analog, logic, validation) and key SOC swim lanes to deliver IP releases on time and with committed content and quality. Monitor program status and risks using data, metrics, and trends, and communicate effectively to engineers, technical leaders, and executives. Identify technical problems and lead solutions drawing on prior design experience. Ensure progress against schedule, recommend recovery actions, and mitigate issues. Drive efficient, effective, and transparent decisions to keep IP execution on track toward aggressive deliverables. Establish and maintain productive, collaborative relationships with peers, partners, and stakeholders across SOC, IP design, and post‑silicon validation teams. Maintain strong connections with other IP execution leads and partners in the US and globally. Conduct retrospective reviews to drive continuous improvements in execution efficiency and product quality. Drive results by inspiring people, role‑modeling Intel values, developing others' capabilities, and ensuring a productive work environment. Skills & Competencies Strong results orientation and aptitude for problem‑solving. Proactive planning for upcoming challenges. Facilitating direct and open communication. Collaborating naturally with a wide range of contributors: technical leads, manager peers, partner teams, senior technologists, and executives. Articulating ideas and key messages succinctly. Demonstrated success leading large‑scale, cross‑functional programs with aggressive timelines and complex external dependencies. Ownership mindset with a high degree of urgency and accountability for execution results and customer success. Solid understanding of the end‑to‑end silicon lifecycle, from architectural definition through production qualification and release. Familiarity with AI/ML‑driven design productivity techniques and automation frameworks. Proven experience executing complex mixed‑signal and/or high‑speed serial IP development in advanced semiconductor process nodes. Excellent communication, documentation, and presentation skills for audiences ranging from individual contributors to technical leaders and executives. Minimum Qualifications Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field with 8+ years of experience. 5+ years of experience managing technical execution for silicon projects. Solid foundational knowledge of analog design principles—including noise, jitter, matching, stability, and linearity. Experience in analog design and IP delivery. Preferred Qualifications Master’s degree in Electrical Engineering, Electronics Engineering, or related field with 6+ years of experience. 8+ years of experience managing technical execution for silicon projects. Proven expertise in analog IP development, delivering from concept to launch with hands‑on experience in analog circuit design, mixed‑signal logic and validation, and physical design. Experience in silicon bring‑up, post‑silicon validation, and lab debug of analog circuits. Deep knowledge of high‑speed serial IO technologies such as PCIe, CXL, USB and of die‑to‑die technologies such as UCIe, BoW, HBM. Equity, Diversity, and Inclusion All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Compensation Annual salary range for jobs performed in the US: $190,610.00 – $269,100.00 USD (individual pay determined by location and additional factors). #J-18808-Ljbffr Intel Corporation