Lead RTL Design Engineer for AI Accelerator
DensityAI
DensityAI is seeking an experienced RTL designer to architect and implement digital blocks for our AI accelerator. You will take microarchitecture concepts through SystemVerilog, synthesize for timing and power, and own blocks end-to-end with DV, PD, and DFT teams toward silicon. You should have 5+ years of designing complex digital blocks/SoCs, strong Verilog/SystemVerilog skills, and experience with memory subsystems and NoC. #J-18808-Ljbffr DensityAI
Vacancy posted 5 days ago
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