Staff DV Engineer

About the Role E-Space is developing low Earth orbit satellite systems for IoT. We are seeking Digital Design Verification Engineers to verify custom ASICs for satellites and wireless telephony. The role focuses on ASIC and RTL verification using Verilog, SystemVerilog, and UVM, with a priority on AI assistance. Responsibilities Strong proficiency in Verilog and SystemVerilog Write and maintain verification tests within an existing UVM verification environment Understand UVM architecture and methodology Write C/C++ code for verification purposes and use Perl or Python for scripting Plan and write test plans, write and maintain verification tests, debug RTL simulations independently Lead design verification efforts at the block level and drive code coverage closure on assigned blocks Qualifications 6+ years of design verification experience in the semiconductor industry Experience with ASIC verification, satellite or wireless telephony environments is preferred Experience in LEO satellite component development, design, and in-orbit activities is a plus Compensation Full time, exempt position based in our Saratoga office. Target base pay $120,000 – $220,000 annually. Total compensation will be determined by experience, knowledge, and skills. Travel & Sponsorship We do not provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Benefits Competitive salaries Continuous learning and development Health and wellness care options Financial solutions for the future Optional legal services (US only) Paid holidays Paid time off #J-18808-Ljbffr Espace