Senior Chip Lead, Physical Design & SoC Innovation

Cadence is seeking a Senior Physical Design Architect/Chip Lead within the Performance Solutions Group (PSG) to drive RTL-to-GDS services for data centers, AI, and automotive markets. You will lead a team, engage directly with customers, and own technical decisions to meet PPAS targets while selecting optimal foundry/node and libraries. Experience with 7nm nodes, Cadence tools, and scripting is essential. You will collaborate across RTL/DFT/CAD teams and promote innovative AI-driven #J-18808-Ljbffr Cadence