Senior ASIC Design Verification Engineer

Seeking a talented Senior ASIC Design Verification Engineer for a full-time remote position, who will develop and execute test plans, create and maintain testbenches, and collaborate with teams to ensure the verification of complex SoCs using SystemVerilog and UVM. Key responsibilities: Develop and execute test plans for RTL designs using SystemVerilog and UVM Create and maintain testbenches, test cases, and test vectors Run simulations to verify design against specifications and debug any identified issues Required qualifications: Bachelor's degree in Electrical or Computer Engineering, Computer Science, or related field Minimum of 8 years of hands-on experience in SoC verification using UVM Experience using Cadence verification tools such as Xcelium, Simvision, and Jasper Proficiency in writing and debugging RTL using SystemVerilog Programming experience using C, C++, and/or Python/Perl