SoC Integration Engineer

About The Role The Unified Intel Chassis (UIC) team develops scalable chassis architectures and Network-on-Chip technologies that power multiple SoCs inside Intel. We create high-performance, reusable IP components that enable product teams to deliver industry-leading performance while optimizing power and area efficiency. We are seeking an experienced SoC Integration Engineer to join our world-class team and work on cutting-edge technology that impacts millions of devices worldwide. What You’ll Do Partner with SoC architecture teams to define and refine system-level chassis and interconnect requirements. Design and integrate high-performance NoC/interconnect fabrics meeting power, performance, and area (PPA) targets. Drive integration of IP blocks into SoC platforms, ensuring scalability and performance across products. Collaborate with fabric IP development teams to enhance or customize reusable components. Analyze trade-offs across performance, power, and area to influence architectural decisions. Work closely with physical design teams to address floor planning and implementation constraints. Support debug, validation, and bring‑up activities for integrated SoC platforms. Collaborate across global, cross‑functional teams to deliver complex silicon solutions. Behavioral Traits That We Are Looking For Systems Thinking: Ability to understand and optimize complex SoC ecosystems end-to-end. Ownership & Accountability: Drives deliverables independently while owning outcomes. Collaboration & Influence: Builds strong partnerships across architecture, design, and global teams across multiple time zones. Technical Leadership: Mentors junior engineers and contributes to technical direction. Problem Solving: Proactively identifies risks and develops scalable solutions. Adaptability: Thrives in a fast-paced, evolving technology environment. Clear Communication: Effectively communicates complex technical concepts across audiences. Qualifications Minimum qualifications required for initial consideration: Bachelor's degree in Electrical Engineering or related field with 6+ years of experience, or a Master's degree in the same field with 4+ years of experience. Experience in SOC and/or IP design. Preferred Qualifications And Experience Experience in microarchitecture and design of IP systems, including 2+ years in fabric design/integration. Expertise in Verilog/System Verilog Design, Lint/CDC/RDC, and timing constraints. Knowledge of AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL. Experience analyzing power, performance and area trade-offs in designs. Experience in physical design to understand floorplan limitations. Benefits Intel invests in our people and offers a complete and competitive package of benefits for employees and their families through every stage of life. Find out more about the benefits of working at Intel. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, California, Santa Clara Additional Locations US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin Business Group The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Compensation Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr Intel