HBM PHY Expert, Annapurna Labs at Annapurna Labs (U.S.) Inc. Austin, TX

DESCRIPTION

We are seeking an HBM/DDRx PHY expert for Annapurna Labs, part of the AWS Utility Computing organization. The role focuses on the definition, design, and validation of next‑generation AWS machine‑learning chips, cards, and server integration, ensuring high‑performance memory interfaces and silicon reliability.

KEY RESPONSIBILITIES

Design and implement innovative next‑generation machine‑learning chips and servers. Collaborate with architects, design teams, and software engineers to deliver the ML chip. Lead IP integration, 2.5D design, bring‑up, characterization, and validation. Work independently with vendors, configure settings, write/modify tests, debug, and collect data across the fleet. Participate in code reviews, design discussions, team planning, and metrics/COE reviews. Mentor junior engineers and contribute to interview processes for the team.

BASIC QUALIFICATIONS

BS or MS in EE, ECE, or CS. 7+ years of silicon development experience, with 3+ years in SOC/IO/Subsystems. Strong understanding of DDR/HBM at the PHY and controller levels. Proficiency in DDR/HBM training, timing parameters, and controller features. Experience driving IP integration and designing silicon and 2.5D packaging. Support physical design team with clocking and timing constraints. Lead cross‑functional triage on complex functional and performance issues. Take leadership in post‑silicon bring‑up of IO and HBM/DRRx stack. Define boot‑up initialization, reset flow, and training sequence. Perform system‑level debugging and root‑cause analysis through bring‑up, characterization, validation, and production phases. Work with third‑party IP and memory vendors. AWS is an equal‑opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or any other protected characteristic. #J-18808-Ljbffr Itlearn360