Analog/Mixed Signal Verilog Modeling Design Engineer

Job Summary Develop Digital-Mixed Signal (DMS) models of analog IPs (touch controller AFEs, wireless power charging, health sensing AFE, satellite AFEs) using SystemVerilog. Interface with analog design and chip DV teams to support analog/mixed‑signal models for chip verification. Understand Verilog-AMS modeling language and SystemVerilog UDT/UDR nettypes (using Cadence wreal or EEnet package). Design analog circuits such as LDOs, TIAs, analog muxing, SAR‑ADC sample‑and‑hold, comparators, DAC voltage converters, buffering and amplification. Write clean RTL for digital design (clock divider, decoder, FSM, etc.) and create testbenches. Run SV vs schematic verification for leaf SV models and use Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor. Use scripting languages (TCL/Perl/Python) and AI tools (Cursor, chipAgents) to generate analog SV models and testbenches based on design specs. Qualifications Bachelor's degree. 8+ years of related experience. Proficiency in SystemVerilog, Verilog‑AMS, and analog/mixed‑signal modeling. Strong knowledge of analog circuit concepts and design. Experience with Cadence development tools and simulation frameworks. Hands‑on scripting skills (TCL, Perl, Python). Comfortable using AI tooling for model generation and testbench creation. Compensation and Benefits Annual base salary range: $120,000 – $192,000. Discretionary annual bonus and equity awards per plan documents. Medical, dental, and vision plans. 401(k) participation with company matching. Employee Stock Purchase Program (ESPP). Employee Assistance Program (EAP). Company‑paid holidays, sick leave, and vacation time. Paid family leave and other applicable leaves of absence. Equal Opportunity Employer Broadcom is a proud equal‑opportunity employer. We consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state, or local law. We also consider applicants with arrest and conviction records consistent with local law. #J-18808-Ljbffr