Director, Cache RTL

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THE ROLE:

AMD’s Cores Organization delivers industry leading CPUs, Caches, and Chiplets that are the foundation of AMD’s server, client, and gaming business.

We are looking for an experienced a Cache RTL Director to lead the Cache Hierarchy (CH) RTL organization responsible for the L2 and L3 cache designs in AMD’s next generation CPU cores. In this role, the candidate will be both the senior technical leader and the people leader for our functional L2 and L3 RTL teams, owning microarchitecture, RTL implementation, and design quality from feature definition through tapeout across multiple concurrent programs and product generations.

The candidate will set the direction for how AMD builds the highest performance, most energy efficient cache designs in the industry.

THE PERSON:

You are a proven leader of leaders with a track record of delivering complex, high-performance cache or CPU designs to production silicon on aggressive schedules.

As the senior microarchitecture and RTL authority for our L2 and L3 caches, you will set technical direction, make and defend difficult performance, power, area, and schedule trade-offs, and maintain a high standard for design quality. We push the envelope on every program, so the status quo must be challenged continuously. This environment requires creativity, innovation, sound judgment, and excellent verbal and written communication skills with engineers, architects, partner organizations, and senior executives.

You are energized by building teams, hiring top talent, developing managers and senior technical leaders, and creating a culture of ownership, collaboration, and accountability. Our team delivers critical designs for multiple AMD products and is growing in both capability and size. You must be able to scale the organization while maintaining focused execution.

KEY RESPONSIBILITIES:

• Lead the functional L2 and L3 cache RTL teams, including first-line managers and senior technical leads, with full ownership of microarchitecture, RTL implementation, and design quality for AMD’s cache hierarchy
• Partner with Cache and CPU Architects to translate architecture into optimized high-performance microarchitecture, and drive feature definition, scoping, and performance/power/area trade-offs across cache controllers, arrays, coherency, and routing fabric
• Own RTL execution across multiple concurrent programs and product generations, including feature enablement plans, milestone commitments, staffing, and schedule; communicate status, risks, and mitigations clearly to senior leadership
• Partner with Physical Design leadership to deliver RTL that is optimized for physical construction, timing closure, and area, and ensure RTL releases support floorplan and tapeout milestones.
• Partner with Design Verification leadership to ensure features are clearly documented, verifiable, and closed with high confidence, and drive objective design-quality metrics across the organization
• Partner with Design For Test and Debug teams to deliver RTL that is reliable, testable, debuggable, and manufacturable
• Work across global teams to resolve complex interactions between core, cache, and SOC/chiplet designs, and drive IP reuse and configurability across server, client, and gaming products
• Champion innovation in design methodology, automation, and AI-assisted engineering to simplify design complexity, improve quality, and increase team productivity
• Recruit, develop, and retain top engineering talent; mentor managers and technical leaders, build succession depth, and foster an inclusive, high-accountability team culture
• Represent the Cache Hierarchy RTL organization in cross-functional, program, and executive reviews. Create technical and program presentations for peers, partners, and management

PREFERRED EXPERIENCE:

• Extensive experience leading RTL and microarchitecture teams, including managing managers, through multiple tapeouts of high-performance CPU, cache, or SOC designs to production silicon
• Deep expertise in Cache architecture development and execution, including Cache Controller and Array RTL implementation
• Prior experience with CPU Coherency, Coherent NOC, Cache Allocation and Replacement Policy, Prefetch interaction, Quality of Service, Fairness and Forward Progress architecture and implementation
• Prior experience with low-power design techniques and RAS features (ECC, error detection and handling) in cache and memory subsystems
• Prior experience executing multiple concurrent programs with shared or configurable IP, and delivering IP to SOC and chiplet integration teams
• Strong command of Digital RTL Design, Verilog/SystemVerilog HDL, design-quality flows (lint, CDC/RDC, formal), and Scripting
• Demonstrated ability to communicate clearly with executives and to collaborate effectively with a diverse team across disciplines and geographies
• Multiple years hardware design experience, including several years of people leadership

ACADEMIC CREDENTIALS:

• Bachelor’s, master’s, or doctoral degree in Electrical Engineering, Computer Science, Computer Engineering, or a similar field.

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.