Sr. Principal Software Engineer

Overview Cadence Design Systems is looking for a highly motivated hardware engineer to work with the Modus R&D engineering team in the Design-For-Test (DFT) IP business unit. As a member of the DFT R&D team, you will design and implement advanced Design‑for‑Test (DFT) hardware, test fabrics, and on‑chip test networks used in next‑generation SoCs. You will contribute to the hardware and software development of industry‑leading test solutions such as scan compression, hierarchical test access architectures, Logic Built-In-Self-Test (LBIST), Memory Built-In-Self-Test (MBIST), Power-On-Self-Test (POST), and In-System Test (IST). Your work will directly support high‑coverage, low‑cost test strategies across complex semiconductor designs. Key Responsibilities Design and implement advanced DFT hardware, test fabrics, and on‑chip test networks. Develop hardware and software for scan compression, hierarchical test access, LBIST, MBIST, POST, and IST. Participate in architecture, microarchitecture, and implementation readiness reviews. Own project execution, including planning, dependency tracking, risk management, milestone ownership, and cross‑functional coordination. Provide technical leadership, mentor senior and junior engineers, and support teams across multiple locations. Required Skills RTL Design & Verification: strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation. Hands‑on coding and automation using SystemVerilog/Verilog, scripting with Perl and Python. Mastery of UVM and directed testbench IP verification, test planning, coverage closure, debugging. Knowledge of network structures and methods for communicating data across an SoC. Full‑flow development & integration: developing complex reusable IPs from architecture through delivery; synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows. IP integration management: requirements review, interface alignment, quality checks, delivery tracking. Debug complex hardware issues across RTL, verification, synthesis, timing, and integration environments. Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral. DFT Architecture: deep understanding of digital design architecture, subsystem integration, DFT, interconnects, memory‑mapped interfaces, reset/clock architecture, low‑power considerations. DFT requirements for SoCs: scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, design‑for‑testability tradeoffs. Knowledge of DFT IP concepts, hardware, and test network communication. Preferred Skills ISO 26262 functional safety concepts, safety mechanisms, diagnostic coverage, safety requirements, ASIL‑oriented design flows. Security‑aware hardware design, secure boot concepts, access control, lifecycle management, key handling, or secure debug. Experience with automotive, industrial, AI, or hyperscaler‑class IP development. Familiarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environments. Driving IP maturity through reusable methodology, quality metrics, and scalable infrastructure. Compensation The annual salary range for California is $196,000 to $364,000.You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Benefits Paid vacation and paid holidays 401(k) plan with employer match Employee stock purchase plan A variety of medical, dental, and vision plan options Other benefits available Equal Employment Opportunity Cadence is committed to equal employment opportunity throughout all levels of the organization. Cadence is proud to be an equal opportunity employer. E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. #J-18808-Ljbffr