Senior Analog/Mixed-Signal Design Engineer (DDR/High-Speed)
Rambus
Rambus Memory Interface Chips BU is seeking a seasoned engineer to lead analog and mixed-signal design for high-speed memory interfaces. You will architect, simulate, and validate receiver, samplers, and signal conditioning circuits, while coordinating with global teams to ensure timely, high-quality results.
Ideal candidates hold an MSEE/Ph.D. with 10+ years in analog/mixed-signal design, with DDR interface experience and Verilog knowledge considered strong assets.
#J-18808-LjbffrVacancy posted 9 hours ago
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