Principal Analog Design Engineer

Responsibilities Own end-to-end analog block development: requirements definition, architecture, transistor-level design, simulation, and signoff Design and optimize analog/mixed-signal circuits such as amplifiers, references, biasing, regulators (LDO/DC‑DC support), comparators, oscillators/clocking, data converters (as applicable), and sensor/AFE front ends Drive performance across PVT corners, mismatch/Monte Carlo, aging/reliability considerations, and realistic loading/interaction with surrounding blocks Partner with layout to guide floorplanning, matching/guarding strategies, parasitic-aware design, and post-layout closure (PEX) Develop and maintain testbenches, modeling collateral, and documentation to enable efficient verification and integration Support silicon bring‑up and debug: correlate lab data to simulations, root‑cause issues, and implement design fixes or ECOs Collaborate cross‑functionally with digital, firmware, DFT, validation, and product engineering to ensure system‑level success Contribute to design methodology improvements: reusable circuits, checklists, signoff flows, and best practices that scale across programs Qualifications 5+ years of experience in analog or mixed-signal IC design (scope and ownership aligned to experience level) Strong fundamentals in analog circuit design, device physics, noise, stability/compensation, and feedback systems Proficiency with industry-standard EDA tools and simulation flows (e.g., Spectre/HSPICE, ADE, waveform/debug tooling) Experience closing designs through post‑layout parasitics and across process/voltage/temperature corners Ability to translate ambiguous system needs into clear block requirements and executable design plans Strong debugging skills and comfort working with lab/validation teams to correlate silicon to simulation Clear communication and high ownership in cross‑site, cross‑functional environments Nice to Have Experience with high‑speed or precision analog (low‑noise, low‑offset, high‑linearity) depending on product needs Background in power management (LDOs, bandgaps, references, protection, start‑up, transient response) ADC/DAC, PLL/clocking, or SERDES‑adjacent analog experience Familiarity with reliability/ESD considerations and design‑for‑manufacturability practices Experience supporting production ramp: yield learning, characterization, and test correlation Success in This Role Looks Like Analog blocks meet spec with margin across PVT, mismatch, and post‑layout effects Design reviews are crisp: requirements, tradeoffs, and risks are clearly articulated and managed Silicon bring‑up converges quickly through strong correlation, structured debug, and decisive fixes Cross‑functional partners (layout, verification, test, validation) can execute efficiently with clear interfaces and documentation Reusable design collateral and improved methodology reduce cycle time and increase first‑pass success Compensation Pay range: 175,000 – 350,000 USD per year (San Jose (HQ)) #J-18808-Ljbffr TylSemi