Senior RTL Engineer, Interconnect Design

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands‑on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring‑up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic‑management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and design integrity, leveraging deep technical and non‑technical leadership skills. Perform substantial direct microarchitecture and RTL coding work. Collaborate with architecture and design team members on the overall solution and execution plan for cutting‑edge large‑scale custom silicon. Work with performance and architecture teams to analyze traffic patterns, identify bottlenecks, and optimize interconnect behavior under realistic system workloads. Collaborate with design verification teams to develop verification strategies, coverage plans, assertions, stress scenarios, and debug approaches for highly concurrent fabric behavior. Partner with physical design teams to ensure interconnect structures are implementable at target frequency, power, and area, including floorplan‑aware design, pipeline strategy, timing closure, and congestion management. Provide technical leadership through design reviews, architecture reviews, documentation, mentoring, and development of reusable RTL and integration methodologies. Leverage experience to help raise the bar on design work inside our team. You might thrive in this role if you have: Extensive industry experience designing and delivering complex SoC interconnect, NoC, coherent fabric, memory subsystem, cache‑coherent, or chip‑level integration solutions. A strong track record of owning major RTL blocks or SoC subsystems from microarchitecture through tape‑out and silicon bring‑up. Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production‑quality RTL. Strong understanding of interconnect concepts such as topology, routing, arbitration, virtual channels, flow control, buffering, ordering, quality of service, coherency, deadlock avoidance, congestion management, and performance monitoring. Experience with common on-chip or chip‑to-chip protocols and interfaces, such as AXI, APB, CXL, PCIe, Ethernet. Experience building custom networking protocols or protocol extensions. Experience working designing and implementing subsystems in the context of large scale systems built with RDMA/RoCE or other HPC‑style system‑level interconnects. Familiarity and deep experience with the full spectrum of industry‑standard RTL‑adjacent development and signoff flows, including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design‑for‑test considerations. Experience working closely with architecture, verification, physical design, firmware, performance, and post‑silicon teams to deliver complex silicon. Strong judgment in making practical design tradeoffs across performance, power, area, schedule, verification risk, and physical implementation constraints. Excellent communication skills and the ability to provide technical direction, mentor engineers, and drive alignment across multiple teams. Passion for achieving high leverage through complexity reduction, automation and creative pragmatism. Preferred Qualifications Experience designing interconnect for AI accelerators, GPUs, CPUs, high‑performance computing systems, networking silicon, or large‑scale datacenter silicon. Experience with memory consistency, virtualization, isolation, RAS, telemetry, or security requirements within complex SoCs. Experience with NoC performance modeling, traffic simulation, emulation, FPGA prototyping, or post‑silicon performance analysis. Experience leading architecture or RTL delivery for first‑generation silicon programs or rapidly evolving hardware platforms. Additional Information To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. Equal Employment Opportunity We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. Reasonable Accommodations We are committed to providing reasonable accommodations to applicants with disabilities. #J-18808-Ljbffr