Senior Physical Design Engineer - Neuromorphic Computing

Job Details:Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.The OpportunityFor nearly a decade, Intel's Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach.Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators.If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads.Position OverviewWe are seeking a senior physical design engineer who is passionate about driving innovation at the intersection of advanced semiconductor technologies, physical AI and next-generation computing architectures. As a member of Intel's neuromorphic silicon team, you will engineer physical integration solutions spanning chiplet and advanced packaging technologies. In this hands-on role, you will help overcome the performance, area, and power limitations of today's AI architectures. You will also lead block- and chip-level closure activities, driving designs to achieve their performance, power, and area targets. An openness to learning new technologies and methodologies, such as asynchronous design techniques and AI-driven automation and debug, is essential.ResponsibilitiesUnderstand system specification to drive down package and die-level requirements.Architect full-chip floorplans and work with designers to set up partition-level floorplans with macro/pin placements and keep-outs.Work with RTL designers to define timing constraints; run synthesis and place-and-route trials; fix timing, EM/IR, LVS and DRC violations.Run back-annotated VCS+SDF simulations and iterate on meeting power/performance targets by providing feedback to designers.Write custom scripts and define tool flows to manipulate synthesis and physical design tools for low power/high performance custom designs.Qualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.Minimum qualificationsBachelors and 6+ years OR Masters and 4+ years of hands-on physical design experience, delivering multiple silicon tape-outs.6+ years of experience in setting up floorplans, defining timing and power constraints and iterating through synthesis, place and route to meet product KPIs.6+ years of experience with scripting languages such as Perl, TCL, Python, etc.4+ years of experience in debugging FEV and RV reports and planning ECOs.2+ years of experience in chiplet integration and/or advanced packaging.1+ year of experience using AI tools for setting up tool flows, debugging and improving overall productivity.Preferred qualificationsStatic timing experience with multiple interfaces (SerDes, UCIe, etc..)Experience in both Cadence (Virtuoso) and Synopsys (Fusion Compiler, Primetime, StarRC, SiliconSmart, VCS) tools.Experience in EDA/CAD software development using object-oriented programming languages like Java or C++.Experience in asynchronous architectures and circuits.Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Folsom, US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, Oregon, Hillsboro; US, California, Folsom; US, California, Santa ClaraType: Full time