CPU Physical Design (RTL to GDS)

Nuvacore is building ground-up high performance, low power CPU for next generation computer workloads. As a member of CPU - specific custom circuit design team, you will enable the design to achieve the target PPA Specifications for the product

THE ROLE

As a CPU Physical Design (PD) Engineer, you will participate in the following :

• Responsible for evaluating RTL and micro-Architecture designs, providing feasibility assessments and actionable feedback.

• Responsible for driving end-to-end design closure from RTL to GDS/Tape-out, ensuring target PPAS (Power, Performance, Area & Schedule) commitments are met.

• Responsible for coordinating and aligning with CAD, RTL/µ-Arch, and other partner teams to ensure seamless execution throughout the design cycle.

• Responsible for leading and influencing the definition and adoption of Tools, Flows, and Methodology (TFM) to drive design efficiency and establish team-wide best practices

WHAT YOU’LL OWN REQUIREMENTS — MUST TO HAVE

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.

• Proficient in industry-standard EDA tools with experience applied to CPU design workflows.

• Demonstrated track record of successfully delivering production-level designs through tape-out.

• Proven experience in PPA optimization across CPU units and design blocks.

• Deep understanding of end-to-end physical design closure, spanning all signoff domains

• Well-versed in timing constraints for both Functional and DFT (Design for Test) modes.

• Strong communication and collaboration skills

REQUIREMENTS — NICE TO HAVE

• Possess substantial years of experience in CPU unit-level implementation

• Demonstrate ability to translate architectural intent into physical design decisions.

• Bring proven experience in PPA-focused design execution for CPUs, including hands-on tool optimization to achieve power, performance, and area targets.

• Hold a deep understanding of Physical Design (PD) signoff checks and methodologies, including FEV, VCLP, EMIR, STA/EXT, and associated closure flows.

• Exhibit thoroughness and precision in ECO (Engineering Change Order) flows,

• Proficient in Python, Perl, or TCL to enhance design productivity and flow efficiency

• Experience in using Agentic AI tools for productivity and automation.

$140,000 - $250,000 a year