CAD Tools Optimisation Engineer (Design Verification)

Description As an experienced CAD engineer, you will assist with delivering high quality infrastructure for automating chip design processes. Specifically as the chip designs are becoming larger than ever, there is a growing need to optimise the performance of simulation tools to maximise the efficiency and reduce resource requirements (both in compute time and space). The scope of work includes developing and deploying new methodologies with vendor and internal teams, supporting and debugging issues on large scale simulations. Minimum Qualifications BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, Computer Science, Software Engineering or a related field Minimum 5 years of experience working on RTL simulation tools Strong foundation on Linux and grid computing systems Knowledge of scripting languages such as Python or Perl Strong interpersonal and analytical skills Ability to work well within a team and be productive under tight schedules Fluency in English Preferred Qualifications Expert knowledge on Cadence tool chain Familiarity with SystemVerilog / Verilog / VHDL A curiosity about GPU / PMU / CPU / SOC architecture and micro-architecture Equal Employment Opportunity At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. #J-18808-Ljbffr Apple Inc.