Principal Engineer-Design (SoC Integration and RTL/IP)

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.Visit our careers page to see what exciting opportunities and company perks await!Job Description:Job SummaryThe dsPIC microcontroller group is seeking an experienced SoC Integration, RTL/IP Design, and FPGA Engineer to lead SoC integration, RTL development, IP design, and FPGA prototyping activities. The candidate will work closely with architecture, verification, and physical design teams to deliver high-quality hardware solutions.Key ResponsibilitiesSoC IntegrationPerform top-level and subsystem integration of processors, memories, peripherals, and custom IPs.Integrate IPs using proprietary bus interfaces and AMBA AXI, AHB / APB protocols.Handle clock/reset integration, interrupt routing, address mapping, and pad / pin connectivity.Resolve chip-level Lint / Synthesis / Timing issues perform CDC / RDC analysis and implement relevant fixesOwnership of post-silicon debug and ECO revisions of the chipRTL and IP DesignDevelop synthesizable RTL using SystemVerilog.Design reusable peripherals, controllers (for memories, ADCs, PWMs), wrappers, and power management modules.Resolve Lint / Synthesis / Timing issues; resolve CDC / RDC errorsPerform RTL reviews, synthesis support, timing optimization, and design debug.Maintenance, enhancements and management of older IPTechnical LeadershipCollaborate with architecture, verification, DFT, physical design, firmware, and system teams.Lead design reviews, mentor junior engineers, and drive technical improvementsHelp with key decisions related to IP and product definition and implementationRequirements/Qualifications:Required SkillsBachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field with 10+ years of experience in ASIC/SoC design, RTL development, FPGA, or SoC integration.Strong knowledge of SystemVerilog and AMBA AXI/AHB/APB protocols.Experience with SoC integration, IP development, clock/reset architecture, and memory mapping.Hands-on experience with Vivado or Quartus, synthesis, STA, and timing closure.Familiarity with simulation tools such as QuestaSim, VCS, or Xcelium.Knowledge of CDC/RDC, RTL lint, and Python/Tcl scripting.Preferred QualificationsExperience with ARM/RISC-V-based SoCs, Ethernet, USB, SPI, I2C, and UART interfaces.Knowledge of low-power design, DFT integration, and Formal-based verification.Experience with FPGA synthesis, place and route, timing closure, constraint development and FPGA-based validation.Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.Expected DeliverablesIntegrated SoC/subsystem RTL and reusable IP modules.FPGA implementation and validation results.Design quality reports and integration documentation.Role Expectation: Independently drive SoC integration, IP design, and FPGA prototyping while providing technical leadership and ensuring robust, reusable hardware designs.Travel Time:0% - 25%Physical Attributes:Hearing, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:Monday - Friday 8 hours/day, Inside: 100%, Sitting: 85%, Standing: 10%, walking: 5%Microchip Technology Incis an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.SummaryLocation: AZ - ChandlerType: Full time