Layout Engineer

Layout Engineer

Apogee Semiconductor provides products and technologies for space and other extreme environments. We are focused on making the frontier of space more accessible by bridging the technology gap between commercial and high-reliability technologies at a lower cost. We provide optimized products and infrastructure that give you the best in reliability and value. Our products and services are targeted towards enabling small-satellites and large constellations that require high performance, a small form factor and radiation resilience at a lower cost. Working in partnership with state-of-the art semiconductor foundries, Apogee Semiconductor develops radiation hardened processes and components that serve as the foundation for our cutting-edge integrated circuits and IP blocks.

As a Layout Engineer, your primary responsibility will be to communicate with project planning and the engineering team any layout related concerns and solutions related to past, current, and future projects. Proactively look for opportunities to improve the layout design cycle from start of project through tapeout. The work location for this job is Plano, Texas.

What You'll Do:

• Layout ownership:
  • Full chip down to "leaf cell" level floor planning and verification.
  • This includes chip boundary, bond out pad locations, block/cell area estimates and pin outs, routing area channels between blocks and power/ground grid development and implementation to minimize losses and EMIR drop across the chip.
  • "Future proofing" floorplans and layouts to allow for faster ECO turn arounds without sacrificing quality or design integrity.
  • ESD cell creation and implementation.
  • Standard cell library development and maintenance depending on PDK/project/design requirements.
  • Document process steps and verification flows throughout project.
  • Deliver weekly status updates on layout related progress.
  • Generate and deliver.gds/.oasis files to Foundry complete and verified full chip layout designs for silicon processing and manufacturing.
• Cross-functional Collaboration:
  • Work closely with Design Engineering Team, Project Design Owner and Foundry to provide schedule estimates and deliverables on time with highest quality, research PDK related limitations or benefits.
  • Work with and support external contractors when appropriate to complete time sensitive deliverables.
• Continuous Improvement:
  • Identify engineering process methodology improvements and implement best practices to enhance the efficiency and effectiveness of layout designs.
  • Identify and enroll in continuous learning opportunities.

Qualifications:

• Associate degree: Engineering Computer Aided Drafting and Design or related IC/PCB Layout certification with 5+ years relevant industry experience in 180 – 22nm technology nodes.
• Solid understanding of semiconductor manufacturing process, and ESD effects and how to mitigate/prevent silicon and design damage.
• Experience with analog and digital specific layout techniques and how/why to use them in various cell designs.
• Knowledge and experience with antenna, cross-talk, cross-coupling, latch-up, and EMIR mitigation techniques.
• Knowledge and experience with Cadence VXL/EXL design software and LVS/DRC verification using PVS, Assura or Calibre, and KiCAD tools.
• Attention to detail and constantly on the lookout for opportunities to improve the design process and quality of layout.
• Excellent communication and interpersonal skills to collaborate effectively with cross-functional teams, customers, and partners.
• Ability to thrive in a fast-paced, dynamic environment and adapt to changing priorities.
• Mentor and train Junior IC Layout engineers to be effective and productive contributors to the company.

Benefits:

All our positions offer a comprehensive compensation package, including equity and robust benefits.

Base pay is part of Apogee Semiconductor's total rewards package, which may include incentive stock options, company-subsidized healthcare, disability and life insurance, flexible PTO, and 401(K) retirement.

Apogee Semiconductor pay ranges are informed and defined through professional grade salary surveys and compensation data sources. The actual base salary offered to a successful candidate will additionally be influenced by a variety of factors including experience, credentials & certifications, educational attainment, skill level requirements, and the level and scope of the position.