Applied Research Engineer, Chip Design (Santa Clara)

NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years! It's an outstanding legacy of innovation that's fueled by phenomenal technology—and outstanding people! We are seeking a world-class engineer to drive applied research at the intersection of AI and ASIC design. Large language models, coding agents, and agentic AI are transforming how chips get designed, and this role puts you at the frontier — applying the latest and greatest AI to NVIDIA's real ASIC design flows and pushing past the limits of what's currently possible. Widely considered one of the technology world's most desirable employers, NVIDIA brings together forward-thinking, hardworking people inventing the future. If you're a creative, collaborative researcher who wants your work to land in real silicon on a real schedule, we want to hear from you.What you'll be doing:Apply LLMs, coding agents, and agentic systems - to core ASIC design problems: RTL generation, Design and Formal verification, PPA prediction and optimization.Hands-on experience with LLMs, RL, RLHF/RLAIF, post-training, evaluation, graders, synthetic data, model training, coding agents, tool-using agents, and production ML systemsDeliver against NVIDIA's internal chip design schedules and activities - your success is measured by how much faster the ASIC teams move, not by research output alone.Build robust data generation (including synthetic data) and meticulous evaluation methodology that separates working systems from demos and use evaluation to decide what to automate next.Wire coding agents and agentic AI into EDA and validation flows — simulation, regressions, waveform and log analysis, script generation — so engineers can drive complex tasks and cut ramp time.Push the limits of what's possible in chip design with models and research harnesses on top of open-source foundations and iterating fast from prototype to production.Partner closely with NVIDIA's internal Nemotron team to improve our models with domain-specific data, feedback, and post-training, feeding ASIC-design expertise back into the models.What we need to see:MS or PhD or equivalent experience in Computer Science, Electrical/Computer Engineering, or related field. 8+ years of proven industry experienceDomain and technical expertise in front-end ASIC (design, verification, timing) combined with project experience applying agentic AI to chip design and optimization problems, with a track record of driving ideas from conception through experimentation to production.Hands-on experience building LLM-based agents or AI tooling that real users depend on context engineering, tool integration, orchestration, and failure analysis, with a focus on evaluation. Experience with custom model training, fine-tuning, or post-training (SFT, RLHF/DPO) over proprietary technical data.Excellent self-motivation, creativity, and a passion for applied research, plus tight-knit collaboration skills and the ability to work effectively within a team.Experience building and maintaining infrastructure (Docker, Slurm, CI/CD, etc.).Excellent written and verbal communication, with proven experience presenting and explaining complex technical work.#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 192,000 USD - 304,750 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until July 27, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time