FPGA Engineer

EOE Statement We are an equal employment opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability status, protected veteran status or any other characteristic protected by law. Full Time Travel required to 10%. Must be able to apply for and maintain a U.S. Government Security Clearance. FPGA Engineer The EndoSec FPGA Engineer is responsible for the design, development, testing, and maintenance of IP cores and FPGA-based systems used in hardware security applications. Tools & Technologies RTL

C/C++

Python VHDL Verilog Tcl Cryptography Hardware Embedded software System Integration Hardware Security Xilinx Simulation IP core Versal Stratix Concept to deployment Vivado GHDL Questa Quartus Prime Zynq Agilex AXI ACE Avalon FPGA verification tools Reverse engineering Cocotb Pyuvm Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA configurations implementing the latest leakage‑resilient hardware cryptography algorithms using state‑of‑the‑art FPGA hardware. Modeling and Simulation: Use simulation tools and verification frameworks to ensure mathematically‑correct logic before hardware deployment. Hardware/Software Design: Work closely with other engineers to integrate FPGA designs with application software and embedded systems. Implement embedded software–based testing solutions where applicable to validate FPGA designs. Performance Optimization: Optimize FPGA designs for timing, resource utilization, and throughput. Identify and resolve system bottlenecks. Testing and Validation: Create comprehensive test and verification plans for FPGA components, conduct unit and integration testing, and validate hardware performance against requirements in a remote environment. System Integration: Ensure seamless integration between internally‑developed and third‑party IP cores, FPGA designs, and embedded systems. Collaborate with other engineers to develop and maintain system‑level architecture. Troubleshooting and Debugging: Utilize debugging tools and techniques to diagnose and resolve issues within FPGA designs and hardware platforms. Documentation: Prepare detailed documentation, including design specifications, testing protocols, and user guides, to support system development and maintenance. Continuous Learning: Actively stay up‑to‑date with the latest advancements in FPGA technology and hardware security to continually refine and enhance system capabilities. Position Requirements Ability to obtain and maintain a U.S. government security clearance. Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. Experience developing FPGA projects and IP cores from concept to deployment, including design, simulation, testing, optimization, release, and maintenance. Proficiency with FPGA design tools (Vivado, Quartus Prime), hardware description languages (VHDL, Verilog), and hardware simulation software (GHDL, Questa). Experience working with programmable SoCs and development platforms from Xilinx or Intel (Versal, Zynq, Agilex, Stratix) and implementing communication between software and hardware. Strong programming skills in scripting languages (Python, Tcl) and C/C++ for hardware/software integration. Experience implementing standard IP core interfaces (AXI, ACE, Avalon). Strong analytical and problem‑solving skills, with the ability to manage complex hardware design issues effectively. Hands‑on experience with hardware testing, instrumentation, and debugging tools (ILA, VIO). Strong documentation skills and the ability to convey complex information clearly and effectively. Collaborative mind‑set and excellent communication skills to work effectively with cross‑functional teams. Preferred Qualifications Advanced degree (M.S. or Ph.D.) in Electrical Engineering, Computer Engineering, or a related field. Knowledge of cryptographic algorithms and experience implementing mathematical algorithms in hardware. Experience in hardware security, tamper detection, and anti‑reverse engineering techniques. Experience with hardware acceleration techniques for computationally intensive tasks. Familiarity with Python‑based FPGA verification tools (cocotb, pyuvm). Position is currently accepting applications. #J-18808-Ljbffr Delphi Technologies