Static Timing Analysis Methodology Engineer/Lead

Job Details:

Job Description:

About Altera:

Accelerating Innovators - Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, SmartNICs and IPUs, offering the flexibility to accelerate innovation.


Our innovation in programmable logic began in 1983. Since then we've delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets.


Join us on our journey to becoming the world's #1 FPGA company!

About the Role:

We are seeking a highly skilled STA Methodology Lead to drive static timing analysis (STA) flows and methodologies across advanced digital design projects. The ideal candidate will have hands-on experience with Synopsys PrimeTime and Cadence Tempus and strong scripting skills (Python, Tcl, Shell, Perl). You will be responsible for developing, maintaining, and enhancing STA methodologies, collaborating with design and CAD teams to ensure timing closure and flow robustness.

Key Responsibilities:

• Develop and support STA flows
  
• Collaborate on timing modeling and methodology improvements
  
• Interface with CAD/DA teams for flow integration
  
• Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing.
  
  
• Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end-to-end testing of the software tools.
  

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$142,600 - $215,000 USD

*We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.*

#LI-MD1

Qualifications:

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of experience in the following skills:

• 8+ years of experience in Static Timing Analysis
  
• 8+ years of experience in Liberty (.lib) model format
  
• 8+ years of experience in methodology and flow development experience
  
• 8+ years of experience Scripting experience (Python, Perl, TCL, shell)
  

Preferred Qualifications:

• Experience with Liberty model characterization and STA-tool-based Liberty model extraction
  
• Familiarity with Fusion Compiler, Innovus, Cadence Pegasus, and other EDA tools
  
• Solid understanding of digital circuit design and simulation
  

Job Type:
Regular

Shift:
Shift 1 (United States of America)

Primary Location:
San Jose, California, United States

Additional Locations:

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.