Design Verification Architect

Job Responsibilities Defines, architects, and documents verification strategy and methodologies for implementing and verifying the silicon design in the most optimal manner. Architects the testbenches and develops universal verification methodology (UVM) or formal based verification approaches. Integrates the block testbench in chip‑level UVM environment and verifies integration. Develops test strategy, test bench architecture, and test plans for design blocks to conform to specifications. Enables interaction with analog and digital teams and supports post‑silicon validation activities. Collaborates with the architecture and design team to create random test generation plans, runs functional simulation to identify gaps in design specification, and conducts failure analysis, coverage analysis, and closure. Defines and develops the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage. Minimum Qualifications Bachelor's degree in Electronics, Computer Engineering, or related field and at least 6+ years of experience OR a Master's degree in the mentioned fields with 4+ years of experience in silicon design development, frontend validation methodologies, simulation environment development (testbench, checker), and simulation/emulation debugging. Proficiency in functional and code coverage closures. Expertise in hardware simulation and validation tools, with strong technical proficiency in C/C++/Python and System Verilog. Familiarity with IP validation tools, processes, and protocols. Preferred Qualifications Experience with OVM/UVM-based test benches and formal verification tools. Deep knowledge of graphics architecture and designs, with an understanding of microarchitectural features. Strong team collaboration skills, problem‑solving ability, and attention to detail. Desire to work on high‑impact projects that challenge and expand your technical capabilities. Compensation Annual Salary Range for jobs which could be performed in the US: $190,610.00 - 269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr Intel