Fab Process Engineering Lead, Raxium

Share Fab Process Engineering Lead, Raxium

corporate_fare Google place Fremont, CA, USA

• Master's degree in Electrical Engineering, Physics, Materials Science, Chemistry or a related field or equivalent practical experience.
• 10 years of experience in semiconductor process engineering in semiconductor wafer fab manufacturing (e.g., patterning and lithography, wafer bonding and CMP, wet chemical processes, plasma processing, etc.).
• 7 years of technical leadership experience.

Preferred qualifications:

• Ph.D in Electrical Engineering, Physics, Materials Science, Chemistry or a related or field equivalent practical experience.
• Black belt of six sigma practitioner.
• 15 years of experience in semiconductor process engineering in high-volume semiconductor wafer fab manufacturing.
• Experience in device fabrication and process integration of semiconductor optoelectronics devices.
• Fab technical leadership experience defining the process robustness strategy and execution, managing engineering cross-functions, influencing senior stakeholders, and managing executive communication.
• Expertise in structured problem-solving, data query and analysis.

About the job

As a Fab Process Engineering Lead, you will be joining our talented team in Silicon Valley. Raxium's technology is based on GaN-on-Si micro LEDs, with more demanding process requirements than found in typical LED fabs, with an installed equipment set to meet those needs.

You will select, motivate, set priorities, develop and manage the individual performance to ensure functional excellence and engaged team members. You'll contribute to the innovation behind products loved by billions worldwide and be a part of a team as we develop a truly novel display technology.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

As a Fab Process Engineering Lead, you will be joining our talented team in Silicon Valley. Raxium's technology is based on GaN-on-Si micro LEDs, with more demanding process requirements than found in typical LED fabs, with an installed equipment set to meet those needs.

You will select, motivate, set priorities, develop and manage the individual performance to ensure functional excellence and engaged team members. You'll contribute to the innovation behind products loved by billions worldwide and be a part of a team as we develop a truly novel display technology.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $236000 - $329000 (USD) + 25% bonus target + equity + benefits

• Own select process engineering areas, ensuring seamless transitions from proof-of-concept to manufacturing, which is now underway. Specific module responsibilities will be dependent on your experience and skillset.
• Drive the strategic wafer fab roadmap and deliver key performance indicators (KPIs) by overseeing process innovation, new tool installations and process capability enhancements. Implement equipment and process optimization to maximize production efficiencies and optimize wafer output.
• Utilize statistical process control (SPC), failure mode and effect analysis (FMEA) and structured problem-solving (RCA) to eliminate systemic bottlenecks and enhance lithography and etch module stability.
• Act as the primary technical liaison for fab operations, ensuring all safety, quality, and manufacturability standards are surpassed.
• Cultivate an engaged, engineering team through proactive performance management and talent development.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.