Staff/Principal Engineer - HBM Design for Test (DFT)

Staff/Principal Engineer – HBM Design For Test (DFT)Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.The Staff/Principal Engineer – HBM Design for Test (DFT) is a senior technical contributor responsible for defining, deploying, and sustaining best-in-class DFT solutions across HBM core die and base die spanning multiple HBM families with a primary focus on logic die MBIST support and architectural definitions along with implementation strategies.This role emphasizes DFT architecture, specification ownership, multi-functional alignment, and program support, supported by strong technical expertise to ensure solutions are robust, scalable, and manufacturable. The role includes close partnership with DFT Verification to ensure feature completeness, coverage, and readiness for tape-out and silicon bring-up.Key ResponsibilitiesEnsure DFT solutions enable high-quality, low-cost, and manufacturable HBM productsDefine, implement, and document logic die MBIST architectures, including controller interaction, access mechanisms, sequencing, and broadcast behavior through high speed logic path design techniques.Own test definitions and DFT entry flows supporting MBIST, logic test, interface test, and debug use cases including customer specified modes of operation.Partner with logic and SoC architects to ensure DFT features are well-integrated, scalable, and generation-over-generation extensibleSupport RTL debug and functional verification for DFT and MBIST related features through the use of Verilog and analog simulation tools.Assist in defining checks, assertions, and coverage expectations related to logic die test functionality.Work with APR teams to support physical implementation of DFT and MBIST logic including:Timing closure for test paths and control logicEvaluation of clocking, reset, and scan/MBIST routing impactsReview of congestion, power, and area tradeoffs related to DFT featuresProvide guidance on DFT-friendly floorplanning and implementation practices, especially for high-fanout or broadcast test structures along with providing scripts to improve efficiency where applicable.Support late-stage implementation and signoff debug related to DFT timing, connectivity, or integration issuesServe as the DFT and MBIST point of contact for assigned programs or functional areasContribute to documentation, knowledge sharing, and training within the DFT and design groups.Mentor junior engineers and support technical skill development within assigned areasMinimum Qualifications:Bachelor's degree in Electrical Engineering or related field (Master's preferred)5+ years of experience in design-for-test, logic test, or related SoC/ASIC design rolesStrong understanding of MBIST fundamentals, memory architectures, and logic test concepts.Working knowledge of memory architectures (HBM or DRAM preferred)Experience influencing DFT requirements, specifications, and verification expectationsPreferred Qualifications:Strong multi-functional collaboration skills, including work with verification organizationsExposure to IEEE 1500 / DFT access mechanisms / broadcast test conceptsExperience supporting first silicon, qualification, or high-volume manufacturing debugClear written and verbal communication skills