Senior Power Integrity (PI) Analysis Engineer

Senior Power Integrity (PI) Analysis Engineer Category: Chip Design Location: San Jose, CA / Austin, TX Experience: More than 6 Years Education: Bachelor's Degree Job Description Power integrity is becoming a first‑order design constraint at advanced technology nodes. As a Senior Power Integrity (PI) Analysis Engineer, you will own IR‑drop sign‑off and power grid implementation for high‑performance CPU blocks, bridging physical design and system‑level power delivery to ensure robust, silicon‑proven voltage margins. Responsibilities Own block‑level IR drop sign‑off (static and dynamic) and power grid implementation for CPU blocks. Set up PI analysis environments, including package models and bump/ball map configurations. Define power grid requirements in close collaboration with physical design teams. Drive power grid architecture decisions to meet sign‑off criteria across all operating points. Deliver CPM models for SoC‑level integration and customer power delivery modeling. Develop, document, and champion advanced PI methodologies through MediaTek’s worldwide PI forum. Collaborate with package, board, and PMIC teams to ensure end‑to‑end power delivery integrity. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of hands‑on power integrity experience on high‑performance CPU or similar high‑speed designs. Deep expertise in static and dynamic IR drop analysis on advanced process nodes (5 nm or below). Experience with hierarchical PI analysis, multi‑voltage domains, and multi‑clock architectures. Knowledge of multi‑OPP sign‑off, including resolving IR/timing conflicts driven by congestion and clock variation. Familiarity with low‑power design methodologies (CPF/UPF, power gating, DVFS). Proficiency with Cadence Voltus and/or Synopsys RedHawk‑SC. Strong scripting skills in Tcl, Python, or Perl. Proven advanced‑node tape‑out experience (sub‑7 nm required; sub‑3 nm a plus). Nice to Have: Power integrity experience with ARM Cortex‑A or custom CPU designs. Familiarity with physical design and STA flows (synthesis, place‑and‑route, timing sign‑off). Experience with package and PCB co‑simulation for power delivery network analysis. Benefits Salary range: $152,400–$254,500 annually. Employee may be eligible for performance bonus, short‑ and long‑term incentive programs. Health insurance coverage, life and disability insurance, savings plan, company‑paid holidays, sick leave, vacation time, parental leave, 401(k). EEO Statement MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #J-18808-Ljbffr MediaTek Research Lab Inc.