ASIC Engineer Intern - Early Career, RTL & Verification
$116.1kNew Grad
New Grad in Seattle is seeking a student graduating by May 2027 to design and implement RTL for digital logic blocks using Verilog or SystemVerilog. You will contribute to verification environments and collaborate across teams to bring features to silicon. The program pays a yearly salary of $116,100 in Seattle/Austin or $133,600 in Cupertino, with benefits including 401(k) matching, mental health support, and medical advisory services. #J-18808-Ljbffr
Vacancy posted 2 days ago
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