Principal ASIC Architect - Memory Systems & AI Interconnects

Job Title: Principal ASIC Architect - Memory Systems & AI InterconnectsJob Location: Santa Clara, CA or Boston, MACompensation: $200K - $300K plus bonus and equityRequirements: ASIC Architecture, Memory Subsystems, CXL / NVLink / PCIe / UCIe/ UALink / RDMA, ARM CHI, AI AcceleratorsOur company is working on solving the memory wall for AI. We develop memory-to-compute networking solutions for AI infrastructure, with a focus on high-bandwidth optical interconnects for XPU memory expansion.Position OverviewWe are seeking a Principal ASIC Architect to lead architecture and system-level design of memory subsystems and AI interconnects for next-generation AI accelerators and SoCs. The role combines deep expertise in memory systems architecture, interconnect protocols (CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe), and performance modeling to define high-bandwidth, low-latency solutions that scale across accelerator, host, and memory fabrics. You will partner with product teams, ASIC design, verification, firmware, and system integration to set architectural direction, drive technical tradeoffs, and ensure robust, high-performance solutions for ML hardware and AI workloads.Key ResponsibilitiesDefine end-to-end memory and interconnect architectures for AI accelerators, including coherent and non-coherent fabrics, memory pooling, and tiered memory hierarchies.Lead specification and micro-architecture of interfaces and protocols (CXL, NVLink, UALink, RDMA, UCIe, PCIe, ARM CHI) and their integration into SoC designs and AI accelerators.Develop performance, latency, and bandwidth models and run system-level simulations to evaluate architectural trade-offs and inform design decisions.Collaborate with RTL, verification, firmware, and physical design teams to translate architecture into implementable hardware blocks and ensure design-for-performance.Drive cross-functional reviews with product management, systems teams, and external IP partners to align on interfaces, compliance, and interoperability.Architect solutions for memory subsystems including HBM, DDR, persistent memory, and CXL-attached devices, optimizing for AI/ML workloads and data movement patterns.Define verification and validation strategies for interconnect and memory subsystems, including test plans for coherence, error handling, flow control, and performance stress tests.Mentor and lead other architects and engineers, setting best practices, architectural patterns, and documentation for memory and interconnect subsystems.Keep abreast of industry trends, emerging protocols, and ecosystem developments; represent the company in standards and partner engagements as needed.Provide technical leadership during silicon bring-up, performance tuning, and system-level debugging to achieve target performance and reliability metrics.QualificationsBachelors degree in Electrical Engineering, Computer Engineering, Computer Science or related field; MS or PhD preferred.10+ years of experience in ASIC/SoC architecture, with a significant focus on memory systems and interconnects for high-performance computing or AI.Deep working knowledge of CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, and PCIe protocols and how they are used to build coherent and high-performance systems.Experience with memory subsystems (HBM, DDR, persistent memory), memory controller architecture, cache coherency and memory consistency models.Hands-on experience with AI accelerators, ML hardware architectures, dataflow characteristics of ML workloads, and integration of accelerators into SoCs.Strong background in performance modeling, system-level simulation, and latency/bandwidth analysis.Familiarity with RTL design concepts, verification methodologies, and silicon bring-up processes; ability to review microarchitecture and RTL for performance implications.Excellent written and verbal communication skills; proven ability to collaborate across teams and influence technical decisions.Proven track record of technical leadership, mentoring engineers, and delivering complex ASIC/SoC projects on schedule.Experience with scripting and modeling tools (Python, C/C++, SystemC, or equivalent) and performance analysis tools is a plus.#EnghpBenefitsCompetitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grantComprehensive benefits including health, dental, vision, and life insuranceWell-equipped, sunny offices in Santa Clara, CA and Boston, MARelocation assistance and visa sponsorshipPerks include a daily lunch stipend, 401k match, and moreA collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing