Senior GPU Inference Performance Engineer (Santa Clara)

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:We are looking for a Senior GPU Inference Performance Engineer to own end-to-end performance analysis of GPU-accelerated AI inference workloads. You will profile, diagnose, and explain performance across the full stack, from GPU silicon through the software runtime, and drive competitive positioning against other accelerator vendors. This role sits at the intersection of hardware, systems software, and AI serving frameworks, and requires someone who can go deep on a trace and present findings to product and executive stakeholders.THE PERSON:A hands-on performance engineer who is equally comfortable reading a GPU trace and briefing executives. You are curious, evidence-driven, rigorous and you don't stop at X is faster, you explain why, rooted in hardware and software evidence. You collaborate across hardware, systems software, and AI serving framework teams, communicate clearly in written reports and presentations, and thrive at the intersection of silicon, systems, and AI.KEY RESPONSIBILITIES:Full-stack GPU profiling: Instrument and analyze inference workloads across AMD Instinct (ROCm, rocProfiler, Omniperf) and NVIDIA (CUDA, Nsight Systems/Compute, DCGM) GPUs. Identify bottlenecks spanning HBM bandwidth, compute utilization, kernel scheduling, memory allocation, and PCIe/Infinity Fabric data movement.AI serving framework performance: Profile and optimize inference engines including vLLM, SGLang, and emerging serving runtimes. Understand KV-cache management, continuous batching, PagedAttention, speculative decoding, and quantization (FP8, MXFP4, INT4) effects on throughput and latency.Competitive performance analysis: Design and execute head-to-head benchmarks (AMD vs. NVIDIA) on standardized LLM workloads. Produce clear, data-backed explanations of why performance differs — attributing gaps to specific hardware features (HBM bandwidth, compute density, interconnect topology), software maturity (kernel libraries, operator fusion, graph compilation), or configuration differences.Multi-server inference networking: Profile and optimize distributed inference topologies including prefill-decode (PD) disaggregation, pipeline parallelism, and tensor parallelism across multi-node clusters. Analyze network-level bottlenecks using RDMA/RoCE traces, NCCL/RCCL collective profiling, and NIC-level counters (Pensando, ConnectX). Quantify the impact of network latency, bandwidth, and congestion on end-to-end inference SLAs.GPU operator and Kubernetes stack: Profile the overhead introduced by GPU operators, device plugins, container runtimes (Docker, containerd), and Kubernetes scheduling on inference latency. Identify and resolve jitter, cold-start, and resource contention issues in production serving environments.Tooling and automation: Build reproducible benchmarking harnesses, profiling scripts, and performance regression dashboards. Automate trace collection and analysis to support continuous performance validation across driver, firmware, and framework updates.PREFERRED EXPERIENCE:Background in GPU performance engineering, HPC, or systems performance analysisHands-on proficiency with either AMD (ROCm, rocProfiler, Omniperf/Omnitrace) or NVIDIA (CUDA, Nsight Systems/Compute, NCU) profiling toolchains, with deep understanding of GPU architecture: warp/wavefront execution, memory hierarchy (registers → LDS/shared → L2 → HBM), occupancy, and instruction-level parallelismExperience profiling vLLM, SGLang, or equivalent LLM serving frameworks, including quantization workflows (FP8, MXFP4, INT4, AWQ, GPTQ) and their performance implicationsExperience with multi-GPU and multi-node inference — tensor parallelism, pipeline parallelism, or PD disaggregation over RDMA/RoCE — including RCCL/NCCL profiling and network tools (perftest, ib_write_bw, tcpdump, Memory Fabric counters)Demonstrated ability to explain performance differences in written reports or presentations — not just X is faster but why, rooted in hardware and software evidenceStrong Python and C/C++ skills; comfort reading GPU kernel code (HIP/CUDA)Experience with Kubernetes GPU scheduling, MIG, and GPU operator performance, or contributions to open-source inference or profiling projectsACADEMIC CREDENTIALS:Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field preferred; advanced degree desiredThis role is not eligible for visa sponsorship.#LI-TB1#LI-HybridBenefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.