Senior FPGA Architect for AI-Driven Hardware
Jobs Paloaltonetworks
Palo Alto Networks is seeking an experienced FPGA/ASIC design engineer to own architecture, RTL, timing closure, and lab bring-up for high‑performance firewall platforms. You will collaborate with software and hardware teams to deliver silicon for next‑generation devices. You’ll synthesize using Vivado/Quartus, verify with FPGA prototyping, and optimize resources while integrating IP blocks such as PCIe, Ethernet, and memory controllers. Strong SystemVerilog & debugging skills are required. #J-18808-Ljbffr Jobs Paloaltonetworks
Vacancy posted 1 day ago
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