Senior/Staff Mid-End Engineer (3D/Process Integration)

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

• Own the WoW stack definition and the TSV / hybrid-bond (HB) interface — partition, bond-pad pitch/array, keep-outs, and alignment budgets — co-defined with the foundry and the memory partner.
• Drive the 3D-aware floorplan inputs: bump/TSV/HB maps, micro-bump and ballmap planning, and die-to-die interface placement, in partnership with Physical Design.
• Define and close DFM and 3D design rules; run design-rule and process-assumption reviews.
• Coordinate thermal and thermal-mechanical (stress / warpage) analysis, and feed mitigations back into floorplan, power delivery, and stack choices.
• Drive 3D signoff: thermal, SI/PI across the die-to-die interface, and known-good-stack assumptions — clean before tapeout.
• Work with DFT on the 3D test strategy (stacked-die test access, IEEE 1838 / known-good-die & known-good-stack) so the integration is testable.
• Manage package / substrate co-design handoff to the OSAT (outsourced): stackup, escape, assembly flow, and yield/reliability considerations.
• Track foundry and memory-partner deliverables and milestones , surface integration risks early, and keep the stack plan aligned with the schedule

• BS/MS/PhD in EE, Materials, Mechanical Engineering, or a related field.
• 5+ years in 3DIC / advanced-packaging / process integration, with at least one product taken to tapeout and through assembly.
• Direct, hands-on experience with TSV and hybrid bonding and a 3D stacking flow (wafer-on-wafer, chip-on-wafer, or SoIC/CoWoS-class).
• Working knowledge of TSMC 3DFabric (SoIC / CoWoS / InFO) or an equivalent foundry 3D ecosystem, including the associated design kits and rule decks.
• Solid grasp of thermal / thermal-mechanical behavior in stacked die and of SI/PI at the die-to-die interface.
• Comfortable owning cross-organization interfaces - foundry, memory IP partner, and OSAT - and translating their constraints into actionable design inputs

• Experience with DRAM-on-logic stacks, HBM-class memory integration, or high-bandwidth memory interfaces.
• Background on AI / HPC accelerators or other high-power, high-bandwidth SoCs.
• Familiarity with thermal/mechanical tools (e.g., Ansys ) and 3D physical/signoff flows (Synopsys / Cadence).
• Exposure to stacked-die test and yield debug.
• Experience standing up a 3D-integration methodology on a small team - comfortable being the first/only specialist in the room.

• You own a genuinely hard, defining problem on the chip - not a slice of someone else's flow.
• Direct line to the foundry and memory partner; your decisions set the stack.
• Early-team seniority with room to shape the 3D methodology and grow the function.

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.