FPGA Verification Engineer, Air Vehicles

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI‑powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting‑edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.

ABOUT THE JOB

We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA . You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight‑critical avionics, with a focus on UVM‑based methodology and coverage‑driven verification. This will require expertise in SystemVerilog, object‑oriented programming, and UVM. If you are someone who has supported rapid avionics development, then this role is for you.

WHAT YOU’LL DO

Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained‑random and transaction-level test sequences to maximize coverage and uncover corner‑case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro‑architecture refinement Support hardware validation and board bring‑up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries

REQUIRED QUALIFICATIONS

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 2+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object‑oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git‑based collaborative workflows including code review Linux development environments Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance

PREFERRED QUALIFICATIONS

5+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety‑critical verification processes SVUnit or equivalent unit‑testing frameworks Formal verification or CDC verification tools Digital interfaces: Ethernet, PCIe, JESD204C, MIL‑STD‑1553, SPI Verification automation scripting (Python, Tcl, Makefile) SoC and ARM‑based embedded platforms Verification automation, CI/CD integration, and Nix‑based build environments US Salary Range: $123,000—$171,000 USD The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril’s total compensation package. Additionally, Anduril offers top‑tier benefits for full‑time employees, including:

BENEFITS

At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. #J-18808-Ljbffr Slope